The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / constants.ll

diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll
index 9d5fb8e637d40ee2c56b801a3910c35e32521e0e..7893df782054ad508520d75797db6f88384eb9bd 100644 (file)
--- a/test/CodeGen/ARM/constants.ll
+++ b/test/CodeGen/ARM/constants.ll
@@ -1,31 +1,46 @@
-; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #0" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #255" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #256" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep ".word.*257" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #-1073741761" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #1008" | wc -l | grep 1
+; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
 
-uint %f1() {
-  ret uint 0
+define i32 @f1() {
+; CHECK: f1
+; CHECK: mov r0, #0
+        ret i32 0
 }
 
-uint %f2() {
-  ret uint 255
+define i32 @f2() {
+; CHECK: f2
+; CHECK: mov r0, #255
+        ret i32 255
 }
 
-uint %f3() {
-  ret uint 256
+define i32 @f3() {
+; CHECK: f3
+; CHECK: mov r0, #1, #24
+        ret i32 256
 }
 
-uint %f4() {
-  ret uint 257
+define i32 @f4() {
+; CHECK: f4
+; CHECK: orr{{.*}}#1, #24
+        ret i32 257
 }
 
-uint %f5() {
-  ret uint 3221225535
+define i32 @f5() {
+; CHECK: f5
+; CHECK: mov r0, #255, #2
+        ret i32 -1073741761
 }
 
-uint %f6() {
-  ret uint 1008
+define i32 @f6() {
+; CHECK: f6
+; CHECK: mov r0, #63, #28
+        ret i32 1008
+}
+
+define void @f7(i32 %a) {
+; CHECK: f7
+; CHECK: cmp r0, #1, #16
+        %b = icmp ugt i32 %a, 65536
+        br i1 %b, label %r, label %r
+r:
+        ret void
 }