The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / constants.ll

diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll
index a66ee41fe1993639b4364cc77a10ff8b6dcde410..7893df782054ad508520d75797db6f88384eb9bd 100644 (file)
--- a/test/CodeGen/ARM/constants.ll
+++ b/test/CodeGen/ARM/constants.ll
@@ -14,31 +14,31 @@ define i32 @f2() {
 
 define i32 @f3() {
 ; CHECK: f3
-; CHECK: mov r0, #1, 24
+; CHECK: mov r0, #1, #24
         ret i32 256
 }
 
 define i32 @f4() {
 ; CHECK: f4
-; CHECK: orr{{.*}}#1, 24
+; CHECK: orr{{.*}}#1, #24
         ret i32 257
 }
 
 define i32 @f5() {
 ; CHECK: f5
-; CHECK: mov r0, #255, 2
+; CHECK: mov r0, #255, #2
         ret i32 -1073741761
 }
 
 define i32 @f6() {
 ; CHECK: f6
-; CHECK: mov r0, #63, 28
+; CHECK: mov r0, #63, #28
         ret i32 1008
 }
 
 define void @f7(i32 %a) {
 ; CHECK: f7
-; CHECK: cmp r0, #1, 16
+; CHECK: cmp r0, #1, #16
         %b = icmp ugt i32 %a, 65536
         br i1 %b, label %r, label %r
 r: