Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / div.ll

diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
index 3f8a752b39fe4a2d0bb06ccb82f1f43d23ac42f1..3d29e05a0ccf2d611c5cb370b3cd18b244c2e2bb 100644 (file)
--- a/test/CodeGen/ARM/div.ll
+++ b/test/CodeGen/ARM/div.ll
@@ -1,29 +1,34 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm > %t
-; RUN: grep __divsi3  %t
-; RUN: grep __udivsi3 %t
-; RUN: grep __modsi3  %t
-; RUN: grep __umodsi3 %t
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=CHECK-ARM
 
-int %f1(int %a, int %b) {
+define i32 @f1(i32 %a, i32 %b) {
 entry:
-       %tmp1 = div int %a, %b
-       ret int %tmp1
+; CHECK-ARM: f1
+; CHECK-ARM: __divsi3
+        %tmp1 = sdiv i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %f2(uint %a, uint %b) {
+define i32 @f2(i32 %a, i32 %b) {
 entry:
-       %tmp1 = div uint %a, %b
-       ret uint %tmp1
+; CHECK-ARM: f2
+; CHECK-ARM: __udivsi3
+        %tmp1 = udiv i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-int %f3(int %a, int %b) {
+define i32 @f3(i32 %a, i32 %b) {
 entry:
-       %tmp1 = rem int %a, %b
-       ret int %tmp1
+; CHECK-ARM: f3
+; CHECK-ARM: __modsi3
+        %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %f4(uint %a, uint %b) {
+define i32 @f4(i32 %a, i32 %b) {
 entry:
-       %tmp1 = rem uint %a, %b
-       ret uint %tmp1
+; CHECK-ARM: f4
+; CHECK-ARM: __umodsi3
+        %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
+