Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / fast-isel-intrinsic.ll

diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll
index f96b5ad3078a59b2ab2277f17dd6595543bc0d8d..3ef8bce5fd055d953b32f358285dab8b2fbd0fc3 100644 (file)
--- a/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -1,3 +1,4 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
@@ -10,7 +11,7 @@ define void @t1() nounwind ssp {
 ; ARM: movw r1, #64
 ; ARM: movw r2, #10
 ; ARM: uxtb r1, r1
-; ARM: bl #14
+; ARM: bl _memset
 ; THUMB: t1
 ; THUMB: ldr.n r0, LCPI0_0
 ; THUMB: adds r0, #5
@@ -32,21 +33,21 @@ define void @t2() nounwind ssp {
 ; ARM: ldr r0, [r0]
 ; ARM: add r1, r0, #4
 ; ARM: add r0, r0, #16
-; ARM: movw r2, #10
+; ARM: movw r2, #17
 ; ARM: str r0, [sp]                @ 4-byte Spill
 ; ARM: mov r0, r1
 ; ARM: ldr r1, [sp]                @ 4-byte Reload
-; ARM: bl #14
+; ARM: bl _memcpy
 ; THUMB: t2
 ; THUMB: ldr.n r0, LCPI1_0
 ; THUMB: ldr r0, [r0]
 ; THUMB: adds r1, r0, #4
 ; THUMB: adds r0, #16
-; THUMB: movs r2, #10
+; THUMB: movs r2, #17
 ; THUMB: movt r2, #0
 ; THUMB: mov r0, r1
 ; THUMB: bl _memcpy
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 17, i32 1, i1 false)
   ret void
 }
 
@@ -60,7 +61,7 @@ define void @t3() nounwind ssp {
 ; ARM: add r0, r0, #16
 ; ARM: movw r2, #10
 ; ARM: mov r0, r1
-; ARM: bl #14
+; ARM: bl _memmove
 ; THUMB: t3
 ; THUMB: ldr.n r0, LCPI2_0
 ; THUMB: ldr r0, [r0]
@@ -74,4 +75,32 @@ define void @t3() nounwind ssp {
   ret void
 }
 
+define void @t4() nounwind ssp {
+; ARM: t4
+; ARM: ldr r0, LCPI3_0
+; ARM: ldr r0, [r0]
+; ARM: ldr r1, LCPI3_1
+; ARM: ldr r1, [r1]
+; ARM: ldr r2, [r1, #16]
+; ARM: str r2, [r0, #4]
+; ARM: ldr r2, [r1, #20]
+; ARM: str r2, [r0, #8]
+; ARM: ldrh r1, [r1, #24]
+; ARM: strh r1, [r0, #12]
+; ARM: bx lr
+; THUMB: ldr.n r0, LCPI3_0
+; THUMB: ldr r0, [r0]
+; THUMB: ldr.n r1, LCPI3_1
+; THUMB: ldr r1, [r1]
+; THUMB: ldr r2, [r1, #16]
+; THUMB: str r2, [r0, #4]
+; THUMB: ldr r2, [r1, #20]
+; THUMB: str r2, [r0, #8]
+; THUMB: ldrh r1, [r1, #24]
+; THUMB: strh r1, [r0, #12]
+; THUMB: bx lr
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  ret void
+}
+
 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind