The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / fast-isel-pred.ll

diff --git a/test/CodeGen/ARM/fast-isel-pred.ll b/test/CodeGen/ARM/fast-isel-pred.ll
index ef436549e87ec428a3fa08a08b3fd89e71d702cc..8de54ad5332bebd9c671d884287a9d7ae77b0f42 100644 (file)
--- a/test/CodeGen/ARM/fast-isel-pred.ll
+++ b/test/CodeGen/ARM/fast-isel-pred.ll
@@ -1,6 +1,4 @@
-; ModuleID = 'test.c'
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
-target triple = "armv7-apple-darwin"
+; RUN: llc -O0 -mtriple=armv7-apple-darwin < %s
 
 define i32 @main() nounwind ssp {
 entry: