MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648

[oota-llvm.git] / test / CodeGen / ARM / fast-isel.ll

diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll
index c8e0211c60c853cfb28a80bbdd421f001558975e..ecd5fe27a4b7a7326b6f0c18acf343d6a105082a 100644 (file)
--- a/test/CodeGen/ARM/fast-isel.ll
+++ b/test/CodeGen/ARM/fast-isel.ll
@@ -145,22 +145,16 @@ define void @test4() {
 ; THUMB: movw r0, :lower16:L_test4g$non_lazy_ptr
 ; THUMB: movt r0, :upper16:L_test4g$non_lazy_ptr
 ; THUMB: ldr r0, [r0]
-; THUMB: ldr r0, [r0]
-; THUMB: adds r0, #1
-; THUMB: movw r1, :lower16:L_test4g$non_lazy_ptr
-; THUMB: movt r1, :upper16:L_test4g$non_lazy_ptr
-; THUMB: ldr r1, [r1]
-; THUMB: str r0, [r1]
+; THUMB: ldr r1, [r0]
+; THUMB: adds r1, #1
+; THUMB: str r1, [r0]
 
 ; ARM: movw r0, :lower16:L_test4g$non_lazy_ptr
 ; ARM: movt r0, :upper16:L_test4g$non_lazy_ptr
 ; ARM: ldr r0, [r0]
-; ARM: ldr r0, [r0]
-; ARM: add r0, r0, #1
-; ARM: movw r1, :lower16:L_test4g$non_lazy_ptr
-; ARM: movt r1, :upper16:L_test4g$non_lazy_ptr
-; ARM: ldr r1, [r1]
-; ARM: str r0, [r1]
+; ARM: ldr r1, [r0]
+; ARM: add r1, r1, #1
+; ARM: str r1, [r0]
 }
 
 ; Check unaligned stores
@@ -223,3 +217,24 @@ entry:
 ; THUMB: vcmpe.f32 s0, #0
   ret i1 %4
 }
+
+; ARM: @urem_fold
+; THUMB: @urem_fold
+; ARM: and r0, r0, #31
+; THUMB: and r0, r0, #31
+define i32 @urem_fold(i32 %a) nounwind {
+  %rem = urem i32 %a, 32
+  ret i32 %rem
+}
+
+define i32 @test7() noreturn nounwind  {
+entry:
+; ARM: @test7
+; THUMB: @test7
+; ARM: trap
+; THUMB: trap
+  tail call void @llvm.trap( )
+  unreachable
+}
+
+declare void @llvm.trap() nounwind