Reapply r155682, making constant folding more consistent, with a fix to work

[oota-llvm.git] / test / CodeGen / ARM / fcopysign.ll

diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
index 1050cd265998b84d216e793eeb9e5ccdb97c7fcc..27fa2b093d8984cbb74cc2f12b560b6d20f38396 100644 (file)
--- a/test/CodeGen/ARM/fcopysign.ll
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
-; RUN: llc < %s -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
+; RUN: llc < %s -disable-post-ra -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
+; RUN: llc < %s -disable-post-ra -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
 
 ; rdar://8984306
 define float @test1(float %x, float %y) nounwind {
@@ -9,9 +9,8 @@ entry:
 ; SOFT: bfi r0, r1, #31, #1
 
 ; HARD: test1:
-; HARD: vabs.f32 d0, d0
-; HARD: cmp r0, #0
-; HARD: vneglt.f32 s0, s0
+; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
+; HARD: vbsl [[REG1]], d
   %0 = tail call float @copysignf(float %x, float %y) nounwind
   ret float %0
 }
@@ -23,9 +22,9 @@ entry:
 ; SOFT: bfi r1, r2, #31, #1
 
 ; HARD: test2:
-; HARD: vabs.f64 d0, d0
-; HARD: cmp r1, #0
-; HARD: vneglt.f64 d0, d0
+; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
+; HARD: vshl.i64 [[REG2]], [[REG2]], #32
+; HARD: vbsl [[REG2]], d1, d0
   %0 = tail call double @copysign(double %x, double %y) nounwind
   ret double %0
 }
@@ -33,13 +32,29 @@ entry:
 define double @test3(double %x, double %y, double %z) nounwind {
 entry:
 ; SOFT: test3:
-; SOFT: vabs.f64
-; SOFT: cmp {{.*}}, #0
-; SOFT: vneglt.f64
+; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
+; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
+; SOFT: vbsl [[REG3]],
   %0 = fmul double %x, %y
   %1 = tail call double @copysign(double %0, double %z) nounwind
   ret double %1
 }
 
+; rdar://9287902
+define float @test4() nounwind {
+entry:
+; SOFT: test4:
+; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
+; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
+; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
+; SOFT: vbsl [[REG6]], [[REG7]], 
+  %0 = tail call double (...)* @bar() nounwind
+  %1 = fptrunc double %0 to float
+  %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
+  %3 = fadd float %1, %2
+  ret float %3
+}
+
+declare double @bar(...)
 declare double @copysign(double, double) nounwind
 declare float @copysignf(float, float) nounwind