Debug Info Testing: use null instead of an empty string in context field.

[oota-llvm.git] / test / CodeGen / ARM / fnmscs.ll

diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll
index c308061734287bc9dd51592665d1340d5597a6bf..78ccb6095e0591f48134705e72b31eedefa93f18 100644 (file)
--- a/test/CodeGen/ARM/fnmscs.ll
+++ b/test/CodeGen/ARM/fnmscs.ll
@@ -7,17 +7,17 @@
 
 define float @t1(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vnmla.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vnmla.f32
 
-; A8U: t1:
+; A8U-LABEL: t1:
 ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
        %0 = fmul float %a, %b
@@ -28,17 +28,17 @@ entry:
 
 define float @t2(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vnmla.f32
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vnmla.f32
 
-; A8U: t2:
+; A8U-LABEL: t2:
 ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
        %0 = fmul float %a, %b
@@ -49,17 +49,17 @@ entry:
 
 define double @t3(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
 ; VFP2: vnmla.f64
 
-; NEON: t3:
+; NEON-LABEL: t3:
 ; NEON: vnmla.f64
 
-; A8U: t3:
+; A8U-LABEL: t3:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t3:
+; A8-LABEL: t3:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
        %0 = fmul double %a, %b
@@ -70,17 +70,17 @@ entry:
 
 define double @t4(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t4:
+; VFP2-LABEL: t4:
 ; VFP2: vnmla.f64
 
-; NEON: t4:
+; NEON-LABEL: t4:
 ; NEON: vnmla.f64
 
-; A8U: t4:
+; A8U-LABEL: t4:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t4:
+; A8-LABEL: t4:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
        %0 = fmul double %a, %b