AMDGPU: Pattern match ffbh pattern to instruction.

[oota-llvm.git] / test / CodeGen / ARM / fpmem.ll

diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
index 13653bbe6aa026372133dd2d01ac5ab7ac0b00e3..23fbea911e5e158cc79c361d4215d6c5413e2118 100644 (file)
--- a/test/CodeGen/ARM/fpmem.ll
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -1,21 +1,40 @@
-; RUN: llvm-as < %s | llc -march=arm | \
-; RUN:   grep {mov r0, #0} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep {flds.*\\\[} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep {fsts.*\\\[} | count 1
+; RUN: llc -mtriple=arm -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
 
 define float @f1(float %a) {
+; CHECK-LABEL: f1:
+; CHECK: mov r0, #0
         ret float 0.000000e+00
 }
 
 define float @f2(float* %v, float %u) {
-        %tmp = load float* %v           ; <float> [#uses=1]
+; CHECK-LABEL: f2:
+; CHECK: vldr{{.*}}[
+        %tmp = load float, float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
         ret float %tmp1
 }
 
+define float @f2offset(float* %v, float %u) {
+; CHECK-LABEL: f2offset:
+; CHECK: vldr{{.*}}, #4]
+        %addr = getelementptr float, float* %v, i32 1
+        %tmp = load float, float* %addr
+        %tmp1 = fadd float %tmp, %u
+        ret float %tmp1
+}
+
+define float @f2noffset(float* %v, float %u) {
+; CHECK-LABEL: f2noffset:
+; CHECK: vldr{{.*}}, #-4]
+        %addr = getelementptr float, float* %v, i32 -1
+        %tmp = load float, float* %addr
+        %tmp1 = fadd float %tmp, %u
+        ret float %tmp1
+}
+
 define void @f3(float %a, float %b, float* %v) {
+; CHECK-LABEL: f3:
+; CHECK: vstr{{.*}}[
         %tmp = fadd float %a, %b         ; <float> [#uses=1]
         store float %tmp, float* %v
         ret void