AMDGPU: Pattern match ffbh pattern to instruction.

[oota-llvm.git] / test / CodeGen / ARM / fpmem.ll

diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
index 8faa57896a8da8eed6e46083748c6df94c51c236..23fbea911e5e158cc79c361d4215d6c5413e2118 100644 (file)
--- a/test/CodeGen/ARM/fpmem.ll
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -1,39 +1,39 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc -mtriple=arm -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
 
 define float @f1(float %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mov r0, #0
         ret float 0.000000e+00
 }
 
 define float @f2(float* %v, float %u) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: vldr{{.*}}[
-        %tmp = load float* %v           ; <float> [#uses=1]
+        %tmp = load float, float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
         ret float %tmp1
 }
 
 define float @f2offset(float* %v, float %u) {
-; CHECK: f2offset:
+; CHECK-LABEL: f2offset:
 ; CHECK: vldr{{.*}}, #4]
-        %addr = getelementptr float* %v, i32 1
-        %tmp = load float* %addr
+        %addr = getelementptr float, float* %v, i32 1
+        %tmp = load float, float* %addr
         %tmp1 = fadd float %tmp, %u
         ret float %tmp1
 }
 
 define float @f2noffset(float* %v, float %u) {
-; CHECK: f2noffset:
+; CHECK-LABEL: f2noffset:
 ; CHECK: vldr{{.*}}, #-4]
-        %addr = getelementptr float* %v, i32 -1
-        %tmp = load float* %addr
+        %addr = getelementptr float, float* %v, i32 -1
+        %tmp = load float, float* %addr
         %tmp1 = fadd float %tmp, %u
         ret float %tmp1
 }
 
 define void @f3(float %a, float %b, float* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: vstr{{.*}}[
         %tmp = fadd float %a, %b         ; <float> [#uses=1]
         store float %tmp, float* %v