The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / ifcvt2.ll

diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll
index 636705beda83ee4097a69c4207632af62434e721..7b9d0cf32cff07f1fd18378f7bff4e23630bf916 100644 (file)
--- a/test/CodeGen/ARM/ifcvt2.ll
+++ b/test/CodeGen/ARM/ifcvt2.ll
@@ -1,9 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
-; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxlt | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxgt | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxge | count 1
+; RUN: llc < %s -march=arm | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK: t1:
+; CHECK: bxlt lr
        %tmp2 = icmp sgt i32 %c, 10
        %tmp5 = icmp slt i32 %d, 4
        %tmp8 = or i1 %tmp5, %tmp2
@@ -20,6 +19,13 @@ UnifiedReturnBlock:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK: t2:
+; CHECK: bxgt lr
+; CHECK: cmp
+; CHECK: addge
+; CHECK: subge
+; CHECK-NOT: bxge lr
+; CHECK: bx lr
        %tmp2 = icmp sgt i32 %c, 10
        %tmp5 = icmp slt i32 %d, 4
        %tmp8 = and i1 %tmp5, %tmp2