The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / ifcvt2.ll

diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll
index d9cac8022b241ff98bf56f94da0ad50aa8a0522a..7b9d0cf32cff07f1fd18378f7bff4e23630bf916 100644 (file)
--- a/test/CodeGen/ARM/ifcvt2.ll
+++ b/test/CodeGen/ARM/ifcvt2.ll
@@ -1,10 +1,8 @@
-; RUN: llc < %s -march=arm > %t
-; RUN: grep bxlt %t | count 1
-; RUN: grep bxgt %t | count 1
-; RUN: not grep bxge %t
-; RUN: not grep bxle %t
+; RUN: llc < %s -march=arm | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK: t1:
+; CHECK: bxlt lr
        %tmp2 = icmp sgt i32 %c, 10
        %tmp5 = icmp slt i32 %d, 4
        %tmp8 = or i1 %tmp5, %tmp2
@@ -21,6 +19,13 @@ UnifiedReturnBlock:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK: t2:
+; CHECK: bxgt lr
+; CHECK: cmp
+; CHECK: addge
+; CHECK: subge
+; CHECK-NOT: bxge lr
+; CHECK: bx lr
        %tmp2 = icmp sgt i32 %c, 10
        %tmp5 = icmp slt i32 %d, 4
        %tmp8 = and i1 %tmp5, %tmp2