-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
; Radar 7449043
%struct.int32x4_t = type { <4 x i32> }
define hidden void @conv4_8_E() nounwind {
entry:
-%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
+%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
unreachable
}
; Radar 9307836 & 9119939
-define double @t7(double %y) nounwind ssp {
+define double @t7(double %y) nounwind {
entry:
; CHECK: t7
; CHECK: flds s15, d0
; Radar 9307836 & 9119939
-define float @t8(float %y) nounwind ssp {
+define float @t8(float %y) nounwind {
entry:
; CHECK: t8
; CHECK: flds s15, s0
%0 = tail call float asm "flds s15, $0", "=t"() nounwind
ret float %0
}
+
+; Radar 9307836 & 9119939
+
+define i32 @t9(i32 %r0) nounwind {
+entry:
+; CHECK: t9
+; CHECK: movw r0, #27182
+ %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
+ ret i32 %0
+}
+
+; Radar 9866494
+
+define void @t10(i8* %f, i32 %g) nounwind {
+entry:
+; CHECK: t10
+; CHECK: str r1, [r0]
+ %f.addr = alloca i8*, align 4
+ store i8* %f, i8** %f.addr, align 4
+ call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
+ ret void
+}
+
+; Radar 10551006
+
+define <4 x i32> @t11(i32* %p) nounwind {
+entry:
+; CHECK: t11
+; CHECK: vld1.s32 {d16[], d17[]}, [r0]
+ %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
+ ret <4 x i32> %0
+}