The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / ldr_ext.ll

diff --git a/test/CodeGen/ARM/ldr_ext.ll b/test/CodeGen/ARM/ldr_ext.ll
index 767f035b4bef9b2c978777c5ba805873dc4905dd..d29eb022baceeb59931c80a5c3d4504babcdea3e 100644 (file)
--- a/test/CodeGen/ARM/ldr_ext.ll
+++ b/test/CodeGen/ARM/ldr_ext.ll
@@ -1,29 +1,37 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldrb"  | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldrsb" | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldrh"  | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldrsh" | wc -l | grep 1
+; RUN: llc < %s -march=arm | FileCheck %s
 
-int %test1(ubyte* %v) {
-       %tmp = load ubyte* %v
-       %tmp1 = cast ubyte %tmp to int
-       ret int %tmp1
+define i32 @test1(i8* %t1) nounwind {
+; CHECK: ldrb
+    %tmp.u = load i8* %t1
+    %tmp1.s = zext i8 %tmp.u to i32
+    ret i32 %tmp1.s
 }
 
-int %test2(ushort* %v) {
-       %tmp = load ushort* %v
-       %tmp1 = cast ushort %tmp to int
-       ret int %tmp1
+define i32 @test2(i16* %t1) nounwind {
+; CHECK: ldrh
+    %tmp.u = load i16* %t1
+    %tmp1.s = zext i16 %tmp.u to i32
+    ret i32 %tmp1.s
 }
 
-int %test3(sbyte* %v) {
-       %tmp = load sbyte* %v
-       %tmp1 = cast sbyte %tmp to int
-       ret int %tmp1
+define i32 @test3(i8* %t0) nounwind {
+; CHECK: ldrsb
+    %tmp.s = load i8* %t0
+    %tmp1.s = sext i8 %tmp.s to i32
+    ret i32 %tmp1.s
 }
 
-int %test4(short* %v) {
-       %tmp = load short* %v
-       %tmp1 = cast short %tmp to int
-       ret int %tmp1
+define i32 @test4(i16* %t0) nounwind {
+; CHECK: ldrsh
+    %tmp.s = load i16* %t0
+    %tmp1.s = sext i16 %tmp.s to i32
+    ret i32 %tmp1.s
+}
+
+define i32 @test5() nounwind {
+; CHECK: mov r0, #0
+; CHECK: ldrsh
+    %tmp.s = load i16* null
+    %tmp1.s = sext i16 %tmp.s to i32
+    ret i32 %tmp1.s
 }