The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / long_shift.ll

diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll
index 45ed2099c95493d32f6e45270f156ffdd23f009f..d5aac2e3ddaf5f86e61d4cb0ee8f35c3c8039712 100644 (file)
--- a/test/CodeGen/ARM/long_shift.ll
+++ b/test/CodeGen/ARM/long_shift.ll
@@ -1,6 +1,4 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
-; XFAIL: *
-; FIXME: Fix after peephole optimizer is fixed.
 
 define i64 @f0(i64 %A, i64 %B) {
 ; CHECK: f0
@@ -26,9 +24,10 @@ define i32 @f2(i64 %x, i64 %y) {
 ; CHECK: f2
 ; CHECK:      lsr{{.*}}r2
 ; CHECK-NEXT: rsb     r3, r2, #32
-; CHECK-NEXT: subs    r2, r2, #32
+; CHECK-NEXT: sub     r2, r2, #32
+; CHECK-NEXT: cmp     r2, #0
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
-; CHECK-NEXT: movge   r0, r1, asr r2
+; CHECK-NEXT: asrge   r0, r1, r2
        %a = ashr i64 %x, %y
        %b = trunc i64 %a to i32
        ret i32 %b
@@ -38,9 +37,10 @@ define i32 @f3(i64 %x, i64 %y) {
 ; CHECK: f3
 ; CHECK:      lsr{{.*}}r2
 ; CHECK-NEXT: rsb     r3, r2, #32
-; CHECK-NEXT: subs    r2, r2, #32
+; CHECK-NEXT: sub     r2, r2, #32
+; CHECK-NEXT: cmp     r2, #0
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
-; CHECK-NEXT: movge   r0, r1, lsr r2
+; CHECK-NEXT: lsrge   r0, r1, r2
        %a = lshr i64 %x, %y
        %b = trunc i64 %a to i32
        ret i32 %b