Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / mul_const.ll

diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll
index 93188cdd883f613378a694f32eefb8c9cf853286..3cb8a8e816f68e4c32b4f2fbd0a8ec0f88042fe8 100644 (file)
--- a/test/CodeGen/ARM/mul_const.ll
+++ b/test/CodeGen/ARM/mul_const.ll
@@ -1,17 +1,43 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
-define i32 @t1(i32 %v) nounwind readnone {
+define i32 @t9(i32 %v) nounwind readnone {
 entry:
-; CHECK: t1:
+; CHECK: t9:
 ; CHECK: add r0, r0, r0, lsl #3
        %0 = mul i32 %v, 9
        ret i32 %0
 }
 
-define i32 @t2(i32 %v) nounwind readnone {
+define i32 @t7(i32 %v) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK: t7:
 ; CHECK: rsb r0, r0, r0, lsl #3
        %0 = mul i32 %v, 7
        ret i32 %0
 }
+
+define i32 @t5(i32 %v) nounwind readnone {
+entry:
+; CHECK: t5:
+; CHECK: add r0, r0, r0, lsl #2
+        %0 = mul i32 %v, 5
+        ret i32 %0
+}
+
+define i32 @t3(i32 %v) nounwind readnone {
+entry:
+; CHECK: t3:
+; CHECK: add r0, r0, r0, lsl #1
+        %0 = mul i32 %v, 3
+        ret i32 %0
+}
+
+define i32 @t12288(i32 %v) nounwind readnone {
+entry:
+; CHECK: t12288:
+; CHECK: add r0, r0, r0, lsl #1
+; CHECK: lsl{{.*}}#12
+        %0 = mul i32 %v, 12288
+        ret i32 %0
+}
+