ARM: Fast-isel register class constrain for extends.

[oota-llvm.git] / test / CodeGen / ARM / ret_arg2.ll

diff --git a/test/CodeGen/ARM/ret_arg2.ll b/test/CodeGen/ARM/ret_arg2.ll
index 365bcd60e7fbeb1c099679ba36b5e6cd23ac718f..84477d042c7499beb2a68087d3cc15f1b66bf06e 100644 (file)
--- a/test/CodeGen/ARM/ret_arg2.ll
+++ b/test/CodeGen/ARM/ret_arg2.ll
@@ -1,4 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm
-int %test(int %a1, int %a2) {
-  ret int %a2
+; RUN: llc < %s -march=arm
+
+define i32 @test(i32 %a1, i32 %a2) {
+        ret i32 %a2
 }
+