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ARM instructions that are both predicated and set the condition codes
[oota-llvm.git]
/
test
/
CodeGen
/
ARM
/
ret_arg4.ll
diff --git
a/test/CodeGen/ARM/ret_arg4.ll
b/test/CodeGen/ARM/ret_arg4.ll
index a9c66e9e98d1ae6ec4662197cdfe7c2718280ed8..f7b3e4a282b2b1fc9f54e0174494a93e0a776114 100644
(file)
--- a/
test/CodeGen/ARM/ret_arg4.ll
+++ b/
test/CodeGen/ARM/ret_arg4.ll
@@
-1,4
+1,4
@@
-; RUN: ll
vm-as < %s | llc
-march=arm
+; RUN: ll
c < %s
-march=arm
define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
ret i32 %a4