The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / sbfx.ll

diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll
index 6f1d87d2c17bd8e5d38c73a72d5add307aa8c949..d29693e4cf9280c72f6e77915b65e5dc24206d4f 100644 (file)
--- a/test/CodeGen/ARM/sbfx.ll
+++ b/test/CodeGen/ARM/sbfx.ll
@@ -12,7 +12,7 @@ entry:
 define i32 @f2(i32 %a) {
 entry:
 ; CHECK: f2:
-; CHECK: ubfx r0, r0, #0, #20
+; CHECK: bfc   r0, #20, #12
     %tmp = shl i32 %a, 12
     %tmp2 = lshr i32 %tmp, 12
     ret i32 %tmp2