Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / shifter_operand.ll

diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll
index 897fb1af01cf59b2676764f172011d196e0a6b68..964cef084f17712fbe23cb8c80b37c9e1ebec633 100644 (file)
--- a/test/CodeGen/ARM/shifter_operand.ll
+++ b/test/CodeGen/ARM/shifter_operand.ll
@@ -36,8 +36,8 @@ entry:
 
 ; lsl #2 is free
 ; A9: test3:
-; A9: ldr r1, [r1, r2, lsl #2]
 ; A9: ldr r0, [r0, r2, lsl #2]
+; A9: ldr r1, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i32*
@@ -51,19 +51,18 @@ entry:
 
 declare i8* @malloc(...)
 
-define fastcc void @test4() nounwind {
+define fastcc void @test4(i16 %addr) nounwind {
 entry:
 ; A8: test4:
-; A8: ldr r1, [r0, r0, lsl #2]
-; A8: str r1, [r0, r0, lsl #2]
+; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A8: str [[REG]], [r0, r1, lsl #2]
 
 ; A9: test4:
-; A9: add r0, r0, r0, lsl #2
-; A9: ldr r1, [r0]
-; A9: str r1, [r0]
+; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A9: str [[REG]], [r0, r1, lsl #2]
   %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
   %1 = bitcast i8* %0 to i32*
-  %2 = sext i16 undef to i32
+  %2 = sext i16 %addr to i32
   %3 = getelementptr inbounds i32* %1, i32 %2
   %4 = load i32* %3, align 4
   %5 = add nsw i32 %4, 1