Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808

[oota-llvm.git] / test / CodeGen / ARM / str_pre-2.ll

diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll
index 983ba455e7b7a4035aa04e69d72ac82442889a0a..5ce2bcecb4766aa36c8e89afaef7ce7ca061c23c 100644 (file)
--- a/test/CodeGen/ARM/str_pre-2.ll
+++ b/test/CodeGen/ARM/str_pre-2.ll
@@ -1,13 +1,12 @@
-; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s
-
-; The greedy register allocator uses a single CSR here, invalidating the test.
+; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s
 
 @b = external global i64*
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-; CHECK: push {lr}
-; CHECK: pop {lr}
+; CHECK: push {r4, r5, lr}
+; CHECK: pop {r4, r5, pc}
+        call void asm sideeffect "", "~{r4},~{r5}"() nounwind
        %0 = load i64** @b, align 4
        %1 = load i64* %0, align 4
        %2 = mul i64 %1, %a