The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / sxt_rot.ll

diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll
index 3f1483b433a21ea6a34e2e90c5062f18f5fa2828..4752f17f1e1c38ad46eb05eae4bb95cde7a19d7f 100644 (file)
--- a/test/CodeGen/ARM/sxt_rot.ll
+++ b/test/CodeGen/ARM/sxt_rot.ll
@@ -1,19 +1,26 @@
-; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 &&
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "sxtb"  | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "sxtab" | wc -l | grep 1
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN:   grep sxtb | count 2
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN:   grep sxtb | grep ror | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN:   grep sxtab | count 1
 
-define i8 @test1(i32 %A) sext {
-       %B = lshr i32 %A, i8 8
-       %C = shl i32 %A, i8 24
+define i32 @test0(i8 %A) {
+        %B = sext i8 %A to i32
+       ret i32 %B
+}
+
+define i8 @test1(i32 %A) signext {
+       %B = lshr i32 %A, 8
+       %C = shl i32 %A, 24
        %D = or i32 %B, %C
        %E = trunc i32 %D to i8
        ret i8 %E
 }
 
-define i32 @test2(i32 %A, i32 %X) sext {
-       %B = lshr i32 %A, i8 8
-       %C = shl i32 %A, i8 24
+define i32 @test2(i32 %A, i32 %X) signext {
+       %B = lshr i32 %A, 8
+       %C = shl i32 %A, 24
        %D = or i32 %B, %C
        %E = trunc i32 %D to i8
         %F = sext i8 %E to i32