The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / sxt_rot.ll

diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll
index bfecce8bde227fe478f479222ffcb7b8a5ede3ae..4752f17f1e1c38ad46eb05eae4bb95cde7a19d7f 100644 (file)
--- a/test/CodeGen/ARM/sxt_rot.ll
+++ b/test/CodeGen/ARM/sxt_rot.ll
@@ -1,8 +1,15 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
-; RUN:   grep sxtb | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN:   grep sxtb | count 2
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN:   grep sxtb | grep ror | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | \
 ; RUN:   grep sxtab | count 1
 
+define i32 @test0(i8 %A) {
+        %B = sext i8 %A to i32
+       ret i32 %B
+}
+
 define i8 @test1(i32 %A) signext {
        %B = lshr i32 %A, 8
        %C = shl i32 %A, 24