AMDGPU: Pattern match ffbh pattern to instruction.

[oota-llvm.git] / test / CodeGen / ARM / trunc_ldr.ll

diff --git a/test/CodeGen/ARM/trunc_ldr.ll b/test/CodeGen/ARM/trunc_ldr.ll
index 0df5fbd06eca19e922e8c3135501f2b076bb7f89..ca7ad9a2fc6233bed92d0b4f9e3866ffa0840a8d 100644 (file)
--- a/test/CodeGen/ARM/trunc_ldr.ll
+++ b/test/CodeGen/ARM/trunc_ldr.ll
@@ -1,27 +1,30 @@
-; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm | grep "ldrb.*7"
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 
        %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
        %struct.B = type { float, float, i32, i32, i32, [0 x i8] }
 
-implementation   ; Functions:
+define i8 @f1(%struct.A* %d) {
+       %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
+       %tmp23 = bitcast i16* %tmp2 to i32*
+       %tmp4 = load i32, i32* %tmp23
+       %tmp512 = lshr i32 %tmp4, 24
+       %tmp56 = trunc i32 %tmp512 to i8
+       ret i8 %tmp56
+}
 
-define i32 @f1(%struct.A* %d) {
-entry:
-       %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
+define i32 @f2(%struct.A* %d) {
+       %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
        %tmp23 = bitcast i16* %tmp2 to i32*
-       %tmp4 = load i32* %tmp23
+       %tmp4 = load i32, i32* %tmp23
        %tmp512 = lshr i32 %tmp4, 24
        %tmp56 = trunc i32 %tmp512 to i8
-       icmp eq i8 %tmp56, 0
-       br i1 %0, label %UnifiedReturnBlock, label %conArue
+        %tmp57 = sext i8 %tmp56 to i32
+       ret i32 %tmp57
+}
 
-conArue:
-       %tmp8 = tail call i32 @f( %struct.A* %d )
-       ret i32 %tmp8
+; CHECK: ldrb{{.*}}7
+; CHECK-NOT: ldrb{{.*}}7
 
-UnifiedReturnBlock:
-       ret i32 0
-}
+; CHECK: ldrsb{{.*}}7
+; CHECK-NOT: ldrsb{{.*}}7
 
-declare i32 @f(%struct.A*)