The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / va_arg.ll

diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll
index a54a499cf19144f3f03dad8a397cf932c0016426..bb4045311624dcc37d426eeb6e0aa5f14a89f1c6 100644 (file)
--- a/test/CodeGen/ARM/va_arg.ll
+++ b/test/CodeGen/ARM/va_arg.ll
@@ -1,10 +1,13 @@
-; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
 ; Test that we correctly align elements when using va_arg
 
-; CHECK: add   r0, r0, #7
-; CHECK: bfc   r0, #0, #3
+; CHECK: test1:
+; CHECK-NOT: bfc
+; CHECK: add   [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
+; CHECK: bfc   [[REG]], #0, #3
+; CHECK-NOT: bfc
 
-define i64 @f8(i32 %i, ...) nounwind optsize {
+define i64 @test1(i32 %i, ...) nounwind optsize {
 entry:
   %g = alloca i8*, align 4
   %g1 = bitcast i8** %g to i8*
@@ -14,6 +17,25 @@ entry:
   ret i64 %0
 }
 
+; CHECK: test2:
+; CHECK-NOT: bfc
+; CHECK: add   [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
+; CHECK: bfc   [[REG]], #0, #3
+; CHECK-NOT:   bfc
+; CHECK: bx    lr
+
+define double @test2(i32 %a, i32 %b, ...) nounwind optsize {
+entry:
+  %ap = alloca i8*, align 4                       ; <i8**> [#uses=3]
+  %ap1 = bitcast i8** %ap to i8*                  ; <i8*> [#uses=2]
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32                       ; <i32> [#uses=0]
+  %1 = va_arg i8** %ap, double                    ; <double> [#uses=1]
+  call void @llvm.va_end(i8* %ap1)
+  ret double %1
+}
+
+
 declare void @llvm.va_start(i8*) nounwind
 
 declare void @llvm.va_end(i8*) nounwind