The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / vbits.ll

diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index 880495dd7fb8d08a131ff032d2eb63f40c52c095..51f9bdf9718b0cf1a5882e63b8f4c7ac316a4783 100644 (file)
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -529,7 +529,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
 define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
 ; CHECK: v_bicimm:
 ; CHECK-NOT: vmov
-; CHECK-NOT vmvn
+; CHECK-NOT: vmvn
 ; CHECK: vbic
        %tmp1 = load <8 x i8>* %A
        %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >