Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / vcgt.ll

diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
index f9260832c2dd516c10c6edcffe3cd3543f5c8d84..2243bac91fb1651b9a71145f653669fc286f0daa 100644 (file)
--- a/test/CodeGen/ARM/vcgt.ll
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -1,13 +1,9 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vcgt\\.s8} %t | count 2
-; RUN: grep {vcgt\\.s16} %t | count 2
-; RUN: grep {vcgt\\.s32} %t | count 2
-; RUN: grep {vcgt\\.u8} %t | count 2
-; RUN: grep {vcgt\\.u16} %t | count 2
-; RUN: grep {vcgt\\.u32} %t | count 2
-; RUN: grep {vcgt\\.f32} %t | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcgts8:
+;CHECK: vcgt.s8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
        %tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
@@ -16,6 +12,8 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcgts16:
+;CHECK: vcgt.s16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
        %tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
@@ -24,6 +22,8 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcgts32:
+;CHECK: vcgt.s32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
        %tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
@@ -32,6 +32,8 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcgtu8:
+;CHECK: vcgt.u8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
        %tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
@@ -40,6 +42,8 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcgtu16:
+;CHECK: vcgt.u16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
        %tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
@@ -48,6 +52,8 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcgtu32:
+;CHECK: vcgt.u32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
        %tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
@@ -56,6 +62,8 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcgtf32:
+;CHECK: vcgt.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = load <2 x float>* %B
        %tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
@@ -64,6 +72,8 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgtQs8:
+;CHECK: vcgt.s8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = load <16 x i8>* %B
        %tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
@@ -72,6 +82,8 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgtQs16:
+;CHECK: vcgt.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i16>* %B
        %tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
@@ -80,6 +92,8 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgtQs32:
+;CHECK: vcgt.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = load <4 x i32>* %B
        %tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
@@ -88,6 +102,8 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgtQu8:
+;CHECK: vcgt.u8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = load <16 x i8>* %B
        %tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
@@ -96,6 +112,8 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgtQu16:
+;CHECK: vcgt.u16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i16>* %B
        %tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
@@ -104,6 +122,8 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgtQu32:
+;CHECK: vcgt.u32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = load <4 x i32>* %B
        %tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
@@ -112,9 +132,67 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vcgtQf32:
+;CHECK: vcgt.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = load <4 x float>* %B
        %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
        ret <4 x i32> %tmp4
 }
+
+define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vacgtf32:
+;CHECK: vacgt.f32
+       %tmp1 = load <2 x float>* %A
+       %tmp2 = load <2 x float>* %B
+       %tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2)
+       ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vacgtQf32:
+;CHECK: vacgt.f32
+       %tmp1 = load <4 x float>* %A
+       %tmp2 = load <4 x float>* %B
+       %tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2)
+       ret <4 x i32> %tmp3
+}
+
+; rdar://7923010
+define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vcgt_zext:
+;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
+;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
+;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
+       %tmp1 = load <4 x float>* %A
+       %tmp2 = load <4 x float>* %B
+       %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
+        %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
+       ret <4 x i32> %tmp4
+}
+
+declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
+;CHECK: vcgti8Z:
+;CHECK-NOT: vmov
+;CHECK-NOT: vmvn
+;CHECK: vcgt.s8
+       %tmp1 = load <8 x i8>* %A
+       %tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+        %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+       ret <8 x i8> %tmp4
+}
+
+define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
+;CHECK: vclti8Z:
+;CHECK-NOT: vmov
+;CHECK-NOT: vmvn
+;CHECK: vclt.s8
+       %tmp1 = load <8 x i8>* %A
+       %tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+        %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+       ret <8 x i8> %tmp4
+}