[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests...

[oota-llvm.git] / test / CodeGen / ARM / vdup.ll

diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 2cf94d63ca143e006ad9538aaf4aefc7b580cfb2..89f355c68751ba59e8d4b617c3829dc930dbfb46 100644 (file)
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -1,7 +1,8 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -verify-machineinstrs %s -o - \
+; RUN: | FileCheck %s
 
 define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK: v_dup8:
+;CHECK-LABEL: v_dup8:
 ;CHECK: vdup.8
        %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
        %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
@@ -15,7 +16,7 @@ define <8 x i8> @v_dup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK: v_dup16:
+;CHECK-LABEL: v_dup16:
 ;CHECK: vdup.16
        %tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
        %tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
@@ -25,7 +26,7 @@ define <4 x i16> @v_dup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK: v_dup32:
+;CHECK-LABEL: v_dup32:
 ;CHECK: vdup.32
        %tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
        %tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
@@ -33,7 +34,7 @@ define <2 x i32> @v_dup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK: v_dupfloat:
+;CHECK-LABEL: v_dupfloat:
 ;CHECK: vdup.32
        %tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
        %tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
@@ -41,7 +42,7 @@ define <2 x float> @v_dupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK: v_dupQ8:
+;CHECK-LABEL: v_dupQ8:
 ;CHECK: vdup.8
        %tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
        %tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
@@ -63,7 +64,7 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK: v_dupQ16:
+;CHECK-LABEL: v_dupQ16:
 ;CHECK: vdup.16
        %tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
        %tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
@@ -77,7 +78,7 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK: v_dupQ32:
+;CHECK-LABEL: v_dupQ32:
 ;CHECK: vdup.32
        %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
        %tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
@@ -87,7 +88,7 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK: v_dupQfloat:
+;CHECK-LABEL: v_dupQfloat:
 ;CHECK: vdup.32
        %tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
        %tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
@@ -99,7 +100,7 @@ define <4 x float> @v_dupQfloat(float %A) nounwind {
 ; Check to make sure it works with shuffles, too.
 
 define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK: v_shuffledup8:
+;CHECK-LABEL: v_shuffledup8:
 ;CHECK: vdup.8
        %tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -107,7 +108,7 @@ define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK: v_shuffledup16:
+;CHECK-LABEL: v_shuffledup16:
 ;CHECK: vdup.16
        %tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
        %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -115,7 +116,7 @@ define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK: v_shuffledup32:
+;CHECK-LABEL: v_shuffledup32:
 ;CHECK: vdup.32
        %tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
        %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -123,7 +124,7 @@ define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK: v_shuffledupfloat:
+;CHECK-LABEL: v_shuffledupfloat:
 ;CHECK: vdup.32
        %tmp1 = insertelement <2 x float> undef, float %A, i32 0
        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -131,7 +132,7 @@ define <2 x float> @v_shuffledupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK: v_shuffledupQ8:
+;CHECK-LABEL: v_shuffledupQ8:
 ;CHECK: vdup.8
        %tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
        %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -139,7 +140,7 @@ define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK: v_shuffledupQ16:
+;CHECK-LABEL: v_shuffledupQ16:
 ;CHECK: vdup.16
        %tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
        %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -147,7 +148,7 @@ define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK: v_shuffledupQ32:
+;CHECK-LABEL: v_shuffledupQ32:
 ;CHECK: vdup.32
        %tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
        %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -155,7 +156,7 @@ define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK: v_shuffledupQfloat:
+;CHECK-LABEL: v_shuffledupQfloat:
 ;CHECK: vdup.32
        %tmp1 = insertelement <4 x float> undef, float %A, i32 0
        %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
@@ -163,7 +164,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
 }
 
 define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK: vduplane8:
+;CHECK-LABEL: vduplane8:
 ;CHECK: vdup.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -171,7 +172,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK: vduplane16:
+;CHECK-LABEL: vduplane16:
 ;CHECK: vdup.16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -179,7 +180,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK: vduplane32:
+;CHECK-LABEL: vduplane32:
 ;CHECK: vdup.32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
@@ -187,7 +188,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK: vduplanefloat:
+;CHECK-LABEL: vduplanefloat:
 ;CHECK: vdup.32
        %tmp1 = load <2 x float>* %A
        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
@@ -195,7 +196,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK: vduplaneQ8:
+;CHECK-LABEL: vduplaneQ8:
 ;CHECK: vdup.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -203,7 +204,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK: vduplaneQ16:
+;CHECK-LABEL: vduplaneQ16:
 ;CHECK: vdup.16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -211,7 +212,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK: vduplaneQ32:
+;CHECK-LABEL: vduplaneQ32:
 ;CHECK: vdup.32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -219,7 +220,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK: vduplaneQfloat:
+;CHECK-LABEL: vduplaneQfloat:
 ;CHECK: vdup.32
        %tmp1 = load <2 x float>* %A
        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -251,7 +252,7 @@ entry:
 }
 
 ; Radar 7373643
-;CHECK: redundantVdup:
+;CHECK-LABEL: redundantVdup:
 ;CHECK: vmov.i8
 ;CHECK-NOT: vdup.8
 ;CHECK: vstr
@@ -263,7 +264,7 @@ define void @redundantVdup(<8 x i8>* %ptr) nounwind {
 }
 
 define <4 x i32> @tdupi(i32 %x, i32 %y) {
-;CHECK: tdupi
+;CHECK-LABEL: tdupi:
 ;CHECK: vdup.32
   %1 = insertelement <4 x i32> undef, i32 %x, i32 0
   %2 = insertelement <4 x i32> %1, i32 %x, i32 1
@@ -273,7 +274,7 @@ define <4 x i32> @tdupi(i32 %x, i32 %y) {
 }
 
 define <4 x float> @tdupf(float %x, float %y) {
-;CHECK: tdupf
+;CHECK-LABEL: tdupf:
 ;CHECK: vdup.32
   %1 = insertelement <4 x float> undef, float %x, i32 0
   %2 = insertelement <4 x float> %1, float %x, i32 1
@@ -285,7 +286,7 @@ define <4 x float> @tdupf(float %x, float %y) {
 ; This test checks that when splatting an element from a vector into another,
 ; the value isn't moved out to GPRs first.
 define <4 x i32> @tduplane(<4 x i32> %invec) {
-;CHECK: tduplane
+;CHECK-LABEL: tduplane:
 ;CHECK-NOT: vmov {{.*}}, d16[1]
 ;CHECK: vdup.32 {{.*}}, d16[1]
   %in = extractelement <4 x i32> %invec, i32 1
@@ -297,7 +298,7 @@ define <4 x i32> @tduplane(<4 x i32> %invec) {
 }
 
 define <2 x float> @check_f32(<4 x float> %v) nounwind {
-;CHECK: check_f32:
+;CHECK-LABEL: check_f32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x float> %v, i32 3
   %1 = insertelement  <2 x float> undef, float %x, i32 0
@@ -306,7 +307,7 @@ define <2 x float> @check_f32(<4 x float> %v) nounwind {
 }
 
 define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
-;CHECK: check_i32:
+;CHECK-LABEL: check_i32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x i32> %v, i32 3
   %1 = insertelement  <2 x i32> undef, i32 %x, i32 0
@@ -315,7 +316,7 @@ define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
 }
 
 define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
-;CHECK: check_i16:
+;CHECK-LABEL: check_i16:
 ;CHECK: vdup.16 {{.*}}, d{{..}}[3]
   %x = extractelement <8 x i16> %v, i32 3
   %1 = insertelement  <4 x i16> undef, i16 %x, i32 0
@@ -324,10 +325,42 @@ define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
 }
 
 define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
-;CHECK: check_i8:
+;CHECK-LABEL: check_i8:
 ;CHECK: vdup.8 {{.*}}, d{{..}}[3]
   %x = extractelement <16 x i8> %v, i32 3
   %1 = insertelement  <8  x i8> undef, i8 %x, i32 0
   %2 = insertelement  <8  x i8> %1, i8 %x, i32 1
   ret <8 x i8> %2
 }
+
+; Check that an SPR splat produces a vdup.
+
+define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
+;CHECK-LABEL: check_spr_splat2:
+;CHECK: vdup.32 d
+  %conv = sitofp i16 %q to float
+  %splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
+  %splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinitializer
+  %sub = fsub <2 x float> %splat.splat, %p
+  ret <2 x float> %sub
+}
+
+define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
+;CHECK-LABEL: check_spr_splat4:
+;CHECK: vdup.32 q
+  %conv = sitofp i16 %q to float
+  %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
+  %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
+  %sub = fsub <4 x float> %splat.splat, %p
+  ret <4 x float> %sub
+}
+
+define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
+;CHECK-LABEL: check_spr_splat4_lane1:
+;CHECK: vdup.32 q{{.*}}, d{{.*}}[1]
+  %conv = sitofp i16 %q to float
+  %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
+  %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %sub = fsub <4 x float> %splat.splat, %p
+  ret <4 x float> %sub
+}