-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
; PR7158
-define arm_aapcs_vfpcc i32 @test_pr7158() nounwind {
+define i32 @test_pr7158() nounwind {
bb.nph55.bb.nph55.split_crit_edge:
br label %bb3
; so they are not split up into i32 values. Radar 8755338.
define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
; CHECK: i64_buildvector
-; CHECK: vldr.64
+; CHECK: vldr
%t0 = load i64* %ptr, align 4
%t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
store <2 x i64> %t1, <2 x i64>* %vp
define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
; CHECK: i64_insertelement
-; CHECK: vldr.64
+; CHECK: vldr
%t0 = load i64* %ptr, align 4
%vec = load <2 x i64>* %vp
%t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
; CHECK: i64_extractelement
-; CHECK: vstr.64
+; CHECK: vstr
%vec = load <2 x i64>* %vp
%t1 = extractelement <2 x i64> %vec, i32 0
store i64 %t1, i64* %ptr
ret void
}
+
+; Test trying to do a AND Combine on illegal types.
+define void @andVec(<3 x i8>* %A) nounwind {
+ %tmp = load <3 x i8>* %A, align 4
+ %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
+ store <3 x i8> %and, <3 x i8>* %A
+ ret void
+}
+
+
+; Test trying to do an OR Combine on illegal types.
+define void @orVec(<3 x i8>* %A) nounwind {
+ %tmp = load <3 x i8>* %A, align 4
+ %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
+ store <3 x i8> %or, <3 x i8>* %A
+ ret void
+}
+
+; The following test was hitting an assertion in the DAG combiner when
+; constant folding the multiply because the "sext undef" was translated to
+; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
+; of the other BUILD_VECTOR.
+define i16 @foldBuildVectors() {
+ %1 = sext <8 x i8> undef to <8 x i16>
+ %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ %3 = extractelement <8 x i16> %2, i32 0
+ ret i16 %3
+}