Implement NEON domain switching for scalar <-> S-register vmovs on ARM

[oota-llvm.git] / test / CodeGen / ARM / vector-extend-narrow.ll

diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
index 5e9239f25632e70e695d24e7e2f248dac86ee2b3..8fd3db29197e878d337cd22d94a2b1ebb4901bf3 100644 (file)
--- a/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -20,7 +20,9 @@ define float @f(<4 x i16>* nocapture %in) {
 
 ; CHECK: g:
 define float @g(<4 x i8>* nocapture %in) {
-  ; CHECK: vldr
+; Note: vld1 here is reasonably important. Mixing VFP and NEON
+; instructions is bad on some cores
+  ; CHECK: vld1
   ; CHECK: vmovl.u8
   ; CHECK: vmovl.u16
   %1 = load <4 x i8>* %in
@@ -44,3 +46,19 @@ define <4 x i8> @h(<4 x float> %v) {
   %1 = fptoui <4 x float> %v to <4 x i8>
   ret <4 x i8> %1
 }
+
+; CHECK: i:
+define <4 x i8> @i(<4 x i8>* %x) {
+; Note: vld1 here is reasonably important. Mixing VFP and NEON
+; instructions is bad on some cores
+  ; CHECK: vld1
+  ; CHECK: vmovl.s8
+  ; CHECK: vmovl.s16
+  ; CHECK: vrecpe
+  ; CHECK: vrecps
+  ; CHECK: vmul
+  ; CHECK: vmovn
+  %1 = load <4 x i8>* %x, align 4
+  %2 = sdiv <4 x i8> zeroinitializer, %1
+  ret <4 x i8> %2
+}