The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / vfp.ll

diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll
index 50000e31e1129d5edbae8a67caa3aa47c311c034..49a69827bc05325f1e3d738b39858a8d48c903e7 100644 (file)
--- a/test/CodeGen/ARM/vfp.ll
+++ b/test/CodeGen/ARM/vfp.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
 
 define void @test(float* %P, double* %D) {
        %A = load float* %P             ; <float> [#uses=1]
@@ -15,11 +16,11 @@ declare double @fabs(double)
 define void @test_abs(float* %P, double* %D) {
 ;CHECK: test_abs:
        %a = load float* %P             ; <float> [#uses=1]
-;CHECK: fabss
+;CHECK: vabs.f32
        %b = call float @fabsf( float %a )              ; <float> [#uses=1]
        store float %b, float* %P
        %A = load double* %D            ; <double> [#uses=1]
-;CHECK: fabsd
+;CHECK: vabs.f64
        %B = call double @fabs( double %A )             ; <double> [#uses=1]
        store double %B, double* %D
        ret void
@@ -39,10 +40,10 @@ define void @test_add(float* %P, double* %D) {
 define void @test_ext_round(float* %P, double* %D) {
 ;CHECK: test_ext_round:
        %a = load float* %P             ; <float> [#uses=1]
-;CHECK: fcvtds
+;CHECK: vcvt.f64.f32
+;CHECK: vcvt.f32.f64
        %b = fpext float %a to double           ; <double> [#uses=1]
        %A = load double* %D            ; <double> [#uses=1]
-;CHECK: fcvtsd
        %B = fptrunc double %A to float         ; <float> [#uses=1]
        store double %b, double* %D
        store float %B, float* %P
@@ -54,7 +55,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
        %a1 = load float* %P1           ; <float> [#uses=1]
        %a2 = load float* %P2           ; <float> [#uses=1]
        %a3 = load float* %P3           ; <float> [#uses=1]
-;CHECK: fmscs
+;CHECK: vnmls.f32
        %X = fmul float %a1, %a2                ; <float> [#uses=1]
        %Y = fsub float %X, %a3         ; <float> [#uses=1]
        store float %Y, float* %P1
@@ -64,7 +65,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
 define i32 @test_ftoi(float* %P1) {
 ;CHECK: test_ftoi:
        %a1 = load float* %P1           ; <float> [#uses=1]
-;CHECK: ftosizs
+;CHECK: vcvt.s32.f32
        %b1 = fptosi float %a1 to i32           ; <i32> [#uses=1]
        ret i32 %b1
 }
@@ -72,7 +73,7 @@ define i32 @test_ftoi(float* %P1) {
 define i32 @test_ftou(float* %P1) {
 ;CHECK: test_ftou:
        %a1 = load float* %P1           ; <float> [#uses=1]
-;CHECK: ftouizs
+;CHECK: vcvt.u32.f32
        %b1 = fptoui float %a1 to i32           ; <i32> [#uses=1]
        ret i32 %b1
 }
@@ -80,7 +81,7 @@ define i32 @test_ftou(float* %P1) {
 define i32 @test_dtoi(double* %P1) {
 ;CHECK: test_dtoi:
        %a1 = load double* %P1          ; <double> [#uses=1]
-;CHECK: ftosizd
+;CHECK: vcvt.s32.f64
        %b1 = fptosi double %a1 to i32          ; <i32> [#uses=1]
        ret i32 %b1
 }
@@ -88,14 +89,14 @@ define i32 @test_dtoi(double* %P1) {
 define i32 @test_dtou(double* %P1) {
 ;CHECK: test_dtou:
        %a1 = load double* %P1          ; <double> [#uses=1]
-;CHECK: ftouizd
+;CHECK: vcvt.u32.f64
        %b1 = fptoui double %a1 to i32          ; <i32> [#uses=1]
        ret i32 %b1
 }
 
 define void @test_utod(double* %P1, i32 %X) {
 ;CHECK: test_utod:
-;CHECK: fuitod
+;CHECK: vcvt.f64.u32
        %b1 = uitofp i32 %X to double           ; <double> [#uses=1]
        store double %b1, double* %P1
        ret void
@@ -103,7 +104,7 @@ define void @test_utod(double* %P1, i32 %X) {
 
 define void @test_utod2(double* %P1, i8 %X) {
 ;CHECK: test_utod2:
-;CHECK: fuitod
+;CHECK: vcvt.f64.u32
        %b1 = uitofp i8 %X to double            ; <double> [#uses=1]
        store double %b1, double* %P1
        ret void
@@ -141,7 +142,7 @@ define void @test_cmpfp0(float* %glob, i32 %X) {
 ;CHECK: test_cmpfp0:
 entry:
        %tmp = load float* %glob                ; <float> [#uses=1]
-;CHECK: fcmpezs
+;CHECK: vcmpe.f32
        %tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00                ; <i1> [#uses=1]
        br i1 %tmp.upgrd.3, label %cond_true, label %cond_false