The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / vfp.ll

diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll
index f58da4409356533e6d95a3b8b5979d7357015240..49a69827bc05325f1e3d738b39858a8d48c903e7 100644 (file)
--- a/test/CodeGen/ARM/vfp.ll
+++ b/test/CodeGen/ARM/vfp.ll
@@ -1,19 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fabs | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fmscs | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fcvt | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fuito | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fto.i | count 4
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep bmi | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep bgt | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN:   grep fcmpezs | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
 
 define void @test(float* %P, double* %D) {
        %A = load float* %P             ; <float> [#uses=1]
@@ -28,16 +14,20 @@ declare float @fabsf(float)
 declare double @fabs(double)
 
 define void @test_abs(float* %P, double* %D) {
+;CHECK: test_abs:
        %a = load float* %P             ; <float> [#uses=1]
+;CHECK: vabs.f32
        %b = call float @fabsf( float %a )              ; <float> [#uses=1]
        store float %b, float* %P
        %A = load double* %D            ; <double> [#uses=1]
+;CHECK: vabs.f64
        %B = call double @fabs( double %A )             ; <double> [#uses=1]
        store double %B, double* %D
        ret void
 }
 
 define void @test_add(float* %P, double* %D) {
+;CHECK: test_add:
        %a = load float* %P             ; <float> [#uses=2]
        %b = fadd float %a, %a          ; <float> [#uses=1]
        store float %b, float* %P
@@ -48,7 +38,10 @@ define void @test_add(float* %P, double* %D) {
 }
 
 define void @test_ext_round(float* %P, double* %D) {
+;CHECK: test_ext_round:
        %a = load float* %P             ; <float> [#uses=1]
+;CHECK: vcvt.f64.f32
+;CHECK: vcvt.f32.f64
        %b = fpext float %a to double           ; <double> [#uses=1]
        %A = load double* %D            ; <double> [#uses=1]
        %B = fptrunc double %A to float         ; <float> [#uses=1]
@@ -58,9 +51,11 @@ define void @test_ext_round(float* %P, double* %D) {
 }
 
 define void @test_fma(float* %P1, float* %P2, float* %P3) {
+;CHECK: test_fma:
        %a1 = load float* %P1           ; <float> [#uses=1]
        %a2 = load float* %P2           ; <float> [#uses=1]
        %a3 = load float* %P3           ; <float> [#uses=1]
+;CHECK: vnmls.f32
        %X = fmul float %a1, %a2                ; <float> [#uses=1]
        %Y = fsub float %X, %a3         ; <float> [#uses=1]
        store float %Y, float* %P1
@@ -68,42 +63,55 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
 }
 
 define i32 @test_ftoi(float* %P1) {
+;CHECK: test_ftoi:
        %a1 = load float* %P1           ; <float> [#uses=1]
+;CHECK: vcvt.s32.f32
        %b1 = fptosi float %a1 to i32           ; <i32> [#uses=1]
        ret i32 %b1
 }
 
 define i32 @test_ftou(float* %P1) {
+;CHECK: test_ftou:
        %a1 = load float* %P1           ; <float> [#uses=1]
+;CHECK: vcvt.u32.f32
        %b1 = fptoui float %a1 to i32           ; <i32> [#uses=1]
        ret i32 %b1
 }
 
 define i32 @test_dtoi(double* %P1) {
+;CHECK: test_dtoi:
        %a1 = load double* %P1          ; <double> [#uses=1]
+;CHECK: vcvt.s32.f64
        %b1 = fptosi double %a1 to i32          ; <i32> [#uses=1]
        ret i32 %b1
 }
 
 define i32 @test_dtou(double* %P1) {
+;CHECK: test_dtou:
        %a1 = load double* %P1          ; <double> [#uses=1]
+;CHECK: vcvt.u32.f64
        %b1 = fptoui double %a1 to i32          ; <i32> [#uses=1]
        ret i32 %b1
 }
 
 define void @test_utod(double* %P1, i32 %X) {
+;CHECK: test_utod:
+;CHECK: vcvt.f64.u32
        %b1 = uitofp i32 %X to double           ; <double> [#uses=1]
        store double %b1, double* %P1
        ret void
 }
 
 define void @test_utod2(double* %P1, i8 %X) {
+;CHECK: test_utod2:
+;CHECK: vcvt.f64.u32
        %b1 = uitofp i8 %X to double            ; <double> [#uses=1]
        store double %b1, double* %P1
        ret void
 }
 
 define void @test_cmp(float* %glob, i32 %X) {
+;CHECK: test_cmp:
 entry:
        %tmp = load float* %glob                ; <float> [#uses=2]
        %tmp3 = getelementptr float* %glob, i32 2               ; <float*> [#uses=1]
@@ -111,6 +119,8 @@ entry:
        %tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4               ; <i1> [#uses=1]
        %tmp5 = fcmp uno float %tmp, %tmp4              ; <i1> [#uses=1]
        %tmp6 = or i1 %tmp.upgrd.1, %tmp5               ; <i1> [#uses=1]
+;CHECK: bmi
+;CHECK-NEXT: bgt
        br i1 %tmp6, label %cond_true, label %cond_false
 
 cond_true:             ; preds = %entry
@@ -129,8 +139,10 @@ declare i32 @bar(...)
 declare i32 @baz(...)
 
 define void @test_cmpfp0(float* %glob, i32 %X) {
+;CHECK: test_cmpfp0:
 entry:
        %tmp = load float* %glob                ; <float> [#uses=1]
+;CHECK: vcmpe.f32
        %tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00                ; <i1> [#uses=1]
        br i1 %tmp.upgrd.3, label %cond_true, label %cond_false