Debug Info: improve the Finder.

[oota-llvm.git] / test / CodeGen / ARM / vld1.ll

diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
index 26543261c1860e388154bed6a784cbfa64226e9b..444d0d5b5edcebdae9bf94db3e08e559782bf95f 100644 (file)
--- a/test/CodeGen/ARM/vld1.ll
+++ b/test/CodeGen/ARM/vld1.ll
@@ -1,31 +1,56 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
-;CHECK: vld1.8 {d0}, [r0, :64]
+;CHECK: vld1.8 {d16}, [r0:64]
        %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
        ret <8 x i8> %tmp1
 }
 
 define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
 ;CHECK: vld1.16
        %tmp0 = bitcast i16* %A to i8*
        %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
        ret <4 x i16> %tmp1
 }
 
+;Check for a post-increment updating load. 
+define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
+;CHECK-LABEL: vld1i16_update:
+;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
+       %A = load i16** %ptr
+       %tmp0 = bitcast i16* %A to i8*
+       %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
+       %tmp2 = getelementptr i16* %A, i32 4
+              store i16* %tmp2, i16** %ptr
+       ret <4 x i16> %tmp1
+}
+
 define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
 ;CHECK: vld1.32
        %tmp0 = bitcast i32* %A to i8*
        %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
        ret <2 x i32> %tmp1
 }
 
+;Check for a post-increment updating load with register increment.
+define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
+;CHECK-LABEL: vld1i32_update:
+;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
+       %A = load i32** %ptr
+       %tmp0 = bitcast i32* %A to i8*
+       %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
+       %tmp2 = getelementptr i32* %A, i32 %inc
+       store i32* %tmp2, i32** %ptr
+       ret <2 x i32> %tmp1
+}
+
 define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
 ;CHECK: vld1.32
        %tmp0 = bitcast float* %A to i8*
        %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
@@ -33,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
 ;CHECK: vld1.64
        %tmp0 = bitcast i64* %A to i8*
        %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
@@ -41,23 +66,35 @@ define <1 x i64> @vld1i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
-;CHECK: vld1.8 {d0, d1}, [r0, :128]
-       %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 32)
+;CHECK: vld1.8 {d16, d17}, [r0:64]
+       %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
+       ret <16 x i8> %tmp1
+}
+
+;Check for a post-increment updating load.
+define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
+;CHECK-LABEL: vld1Qi8_update:
+;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
+       %A = load i8** %ptr
+       %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
+       %tmp2 = getelementptr i8* %A, i32 16
+       store i8* %tmp2, i8** %ptr
        ret <16 x i8> %tmp1
 }
 
 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
-;CHECK: vld1.16
+;CHECK-LABEL: vld1Qi16:
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld1.16 {d16, d17}, [r0:128]
        %tmp0 = bitcast i16* %A to i8*
-       %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 1)
+       %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32)
        ret <8 x i16> %tmp1
 }
 
 define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
 ;CHECK: vld1.32
        %tmp0 = bitcast i32* %A to i8*
        %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
@@ -65,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
 ;CHECK: vld1.32
        %tmp0 = bitcast float* %A to i8*
        %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
@@ -73,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind {
 }
 
 define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
 ;CHECK: vld1.64
        %tmp0 = bitcast i64* %A to i8*
        %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
@@ -96,8 +133,6 @@ declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
 ; Do not crash if the vld1 result is not used.
 define void @unused_vld1_result() {
 entry:
-;CHECK: unused_vld1_result
-;CHECK: vld1.32
   %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) 
   call void @llvm.trap()
   unreachable