Two sets of changes. Sorry they are intermingled.

[oota-llvm.git] / test / CodeGen / ARM / vmul.ll

diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll
index 325da5deabe514a27afe06bd6b07fdd92572c375..5383425018f8e37c00b9f4dfa6338e24d95f5ba7 100644 (file)
--- a/test/CodeGen/ARM/vmul.ll
+++ b/test/CodeGen/ARM/vmul.ll
@@ -32,7 +32,7 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: vmul.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = load <2 x float>* %B
-       %tmp3 = mul <2 x float> %tmp1, %tmp2
+       %tmp3 = fmul <2 x float> %tmp1, %tmp2
        ret <2 x float> %tmp3
 }
 
@@ -77,7 +77,7 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: vmul.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = load <4 x float>* %B
-       %tmp3 = mul <4 x float> %tmp1, %tmp2
+       %tmp3 = fmul <4 x float> %tmp1, %tmp2
        ret <4 x float> %tmp3
 }
 
@@ -152,8 +152,10 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vmull.s8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
+       %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+       %tmp5 = mul <8 x i16> %tmp3, %tmp4
+       ret <8 x i16> %tmp5
 }
 
 define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -161,8 +163,10 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vmull.s16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
+       %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+       %tmp5 = mul <4 x i32> %tmp3, %tmp4
+       ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -170,8 +174,10 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vmull.s32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
+       %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+       %tmp5 = mul <2 x i64> %tmp3, %tmp4
+       ret <2 x i64> %tmp5
 }
 
 define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -179,8 +185,10 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vmull.u8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
+       %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+       %tmp5 = mul <8 x i16> %tmp3, %tmp4
+       ret <8 x i16> %tmp5
 }
 
 define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -188,8 +196,10 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vmull.u16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
+       %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+       %tmp5 = mul <4 x i32> %tmp3, %tmp4
+       ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -197,8 +207,10 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vmull.u32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
+       %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+       %tmp5 = mul <2 x i64> %tmp3, %tmp4
+       ret <2 x i64> %tmp5
 }
 
 define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -215,8 +227,10 @@ entry:
 ; CHECK: test_vmull_lanes16
 ; CHECK: vmull.s16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
-  %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
-  ret <4 x i32> %1
+  %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32>
+  %2 = sext <4 x i16> %0 to <4 x i32>
+  %3 = mul <4 x i32> %1, %2
+  ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
@@ -224,8 +238,10 @@ entry:
 ; CHECK: test_vmull_lanes32
 ; CHECK: vmull.s32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
-  %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %1
+  %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64>
+  %2 = sext <2 x i32> %0 to <2 x i64>
+  %3 = mul <2 x i64> %1, %2
+  ret <2 x i64> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
@@ -233,8 +249,10 @@ entry:
 ; CHECK: test_vmull_laneu16
 ; CHECK: vmull.u16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
-  %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
-  ret <4 x i32> %1
+  %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>
+  %2 = zext <4 x i16> %0 to <4 x i32>
+  %3 = mul <4 x i32> %1, %2
+  ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
@@ -242,16 +260,10 @@ entry:
 ; CHECK: test_vmull_laneu32
 ; CHECK: vmull.u32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
-  %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %1
+  %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>
+  %2 = zext <2 x i32> %0 to <2 x i64>
+  %3 = mul <2 x i64> %1, %2
+  ret <2 x i64> %3
 }
 
-declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
 declare <8 x i16>  @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone