Temporarily disable Hexagon tests. They are failing on OS X

[oota-llvm.git] / test / CodeGen / ARM / vrev.ll

diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll
index 994d89d31c7813557dacb25de353a435cc350c25..e154334970b7d29802624529b8946806136eb5da 100644 (file)
--- a/test/CodeGen/ARM/vrev.ll
+++ b/test/CodeGen/ARM/vrev.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
-define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 ;CHECK: test_vrev64D8:
 ;CHECK: vrev64.8
        %tmp1 = load <8 x i8>* %A
@@ -8,7 +8,7 @@ define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
        ret <8 x i8> %tmp2
 }
 
-define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
+define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 ;CHECK: test_vrev64D16:
 ;CHECK: vrev64.16
        %tmp1 = load <4 x i16>* %A
@@ -16,7 +16,7 @@ define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
        ret <4 x i16> %tmp2
 }
 
-define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
+define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 ;CHECK: test_vrev64D32:
 ;CHECK: vrev64.32
        %tmp1 = load <2 x i32>* %A
@@ -24,7 +24,7 @@ define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
        ret <2 x i32> %tmp2
 }
 
-define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
+define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 ;CHECK: test_vrev64Df:
 ;CHECK: vrev64.32
        %tmp1 = load <2 x float>* %A
@@ -32,7 +32,7 @@ define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
        ret <2 x float> %tmp2
 }
 
-define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 ;CHECK: test_vrev64Q8:
 ;CHECK: vrev64.8
        %tmp1 = load <16 x i8>* %A
@@ -40,7 +40,7 @@ define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
        ret <16 x i8> %tmp2
 }
 
-define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
+define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 ;CHECK: test_vrev64Q16:
 ;CHECK: vrev64.16
        %tmp1 = load <8 x i16>* %A
@@ -48,7 +48,7 @@ define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
        ret <8 x i16> %tmp2
 }
 
-define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
+define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 ;CHECK: test_vrev64Q32:
 ;CHECK: vrev64.32
        %tmp1 = load <4 x i32>* %A
@@ -56,7 +56,7 @@ define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
        ret <4 x i32> %tmp2
 }
 
-define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
+define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 ;CHECK: test_vrev64Qf:
 ;CHECK: vrev64.32
        %tmp1 = load <4 x float>* %A
@@ -64,7 +64,7 @@ define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
        ret <4 x float> %tmp2
 }
 
-define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 ;CHECK: test_vrev32D8:
 ;CHECK: vrev32.8
        %tmp1 = load <8 x i8>* %A
@@ -72,7 +72,7 @@ define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
        ret <8 x i8> %tmp2
 }
 
-define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
+define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 ;CHECK: test_vrev32D16:
 ;CHECK: vrev32.16
        %tmp1 = load <4 x i16>* %A
@@ -80,7 +80,7 @@ define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
        ret <4 x i16> %tmp2
 }
 
-define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 ;CHECK: test_vrev32Q8:
 ;CHECK: vrev32.8
        %tmp1 = load <16 x i8>* %A
@@ -88,7 +88,7 @@ define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
        ret <16 x i8> %tmp2
 }
 
-define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
+define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 ;CHECK: test_vrev32Q16:
 ;CHECK: vrev32.16
        %tmp1 = load <8 x i16>* %A
@@ -96,7 +96,7 @@ define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
        ret <8 x i16> %tmp2
 }
 
-define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 ;CHECK: test_vrev16D8:
 ;CHECK: vrev16.8
        %tmp1 = load <8 x i8>* %A
@@ -104,10 +104,79 @@ define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
        ret <8 x i8> %tmp2
 }
 
-define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ;CHECK: test_vrev16Q8:
 ;CHECK: vrev16.8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
        ret <16 x i8> %tmp2
 }
+
+; Undef shuffle indices should not prevent matching to VREV:
+
+define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
+;CHECK: test_vrev64D8_undef:
+;CHECK: vrev64.8
+       %tmp1 = load <8 x i8>* %A
+       %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
+       ret <8 x i8> %tmp2
+}
+
+define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
+;CHECK: test_vrev32Q16_undef:
+;CHECK: vrev32.16
+       %tmp1 = load <8 x i16>* %A
+       %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
+       ret <8 x i16> %tmp2
+}
+
+; A vcombine feeding a VREV should not obscure things.  Radar 8597007.
+
+define void @test_with_vcombine(<4 x float>* %v) nounwind {
+;CHECK: test_with_vcombine:
+;CHECK-NOT: vext
+;CHECK: vrev64.32
+  %tmp1 = load <4 x float>* %v, align 16
+  %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
+  %tmp3 = extractelement <2 x double> %tmp2, i32 0
+  %tmp4 = bitcast double %tmp3 to <2 x float>
+  %tmp5 = extractelement <2 x double> %tmp2, i32 1
+  %tmp6 = bitcast double %tmp5 to <2 x float>
+  %tmp7 = fadd <2 x float> %tmp6, %tmp6
+  %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  store <4 x float> %tmp8, <4 x float>* %v, align 16
+  ret void
+}
+
+; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
+; to <2 x i16> when stored to memory. Currently ARM scalarizes these stores.
+; See PR 11158
+define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
+; CHECK: test_vrev64:
+; CHECK: vst1.16
+; CHECK: vst1.16
+entry:
+  %0 = bitcast <4 x i16>* %source to <8 x i16>*
+  %tmp2 = load <8 x i16>* %0, align 4
+  %tmp3 = extractelement <8 x i16> %tmp2, i32 6
+  %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
+  %tmp9 = extractelement <8 x i16> %tmp2, i32 5
+  %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
+  store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
+  ret void
+}
+
+; Test vrev of float4
+define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
+; CHECK: float_vrev64
+; CHECK: vext.32
+; CHECK: vrev64.32
+entry:
+  %0 = bitcast float* %source to <4 x float>*
+  %tmp2 = load <4 x float>* %0, align 4
+  %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
+  %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
+  store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
+  ret void
+}
+