The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / vstlane.ll

diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll
index 9aa8d59a289c3b2c36f349da62de6486851f123d..d1bc15ad576da687cbafe01ebf7330ed3319ea31 100644 (file)
--- a/test/CodeGen/ARM/vstlane.ll
+++ b/test/CodeGen/ARM/vstlane.ll
@@ -10,6 +10,19 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
        ret void
 }
 
+;Check for a post-increment updating store.
+define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
+;CHECK: vst1lanei8_update:
+;CHECK: vst1.8 {d16[3]}, [r2]!
+       %A = load i8** %ptr
+       %tmp1 = load <8 x i8>* %B
+       %tmp2 = extractelement <8 x i8> %tmp1, i32 3
+       store i8 %tmp2, i8* %A, align 8
+       %tmp3 = getelementptr i8* %A, i32 1
+       store i8* %tmp3, i8** %ptr
+       ret void
+}
+
 define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vst1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
@@ -66,6 +79,19 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
        ret void
 }
 
+;Check for a post-increment updating store.
+define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
+;CHECK: vst1laneQi32_update:
+;CHECK: vst1.32 {d17[1]}, [r1, :32]!
+       %A = load i32** %ptr
+       %tmp1 = load <4 x i32>* %B
+       %tmp2 = extractelement <4 x i32> %tmp1, i32 3
+       store i32 %tmp2, i32* %A, align 8
+       %tmp3 = getelementptr i32* %A, i32 1
+       store i32* %tmp3, i32** %ptr
+       ret void
+}
+
 define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK: vst1laneQf:
 ;CHECK: vst1.32 {d17[1]}, [r0]
@@ -94,6 +120,19 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
        ret void
 }
 
+;Check for a post-increment updating store with register increment.
+define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
+;CHECK: vst2lanei16_update:
+;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
+       %A = load i16** %ptr
+       %tmp0 = bitcast i16* %A to i8*
+       %tmp1 = load <4 x i16>* %B
+       call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
+       %tmp2 = getelementptr i16* %A, i32 %inc
+       store i16* %tmp2, i16** %ptr
+       ret void
+}
+
 define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vst2lanei32:
 ;CHECK: vst2.32
@@ -205,6 +244,19 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
        ret void
 }
 
+;Check for a post-increment updating store.
+define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
+;CHECK: vst3laneQi32_update:
+;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
+       %A = load i32** %ptr
+       %tmp0 = bitcast i32* %A to i8*
+       %tmp1 = load <4 x i32>* %B
+       call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
+       %tmp2 = getelementptr i32* %A, i32 3
+       store i32* %tmp2, i32** %ptr
+       ret void
+}
+
 define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK: vst3laneQf:
 ;CHECK: vst3.32
@@ -233,6 +285,18 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
        ret void
 }
 
+;Check for a post-increment updating store.
+define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
+;CHECK: vst4lanei8_update:
+;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]!
+       %A = load i8** %ptr
+       %tmp1 = load <8 x i8>* %B
+       call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
+       %tmp2 = getelementptr i8* %A, i32 4
+       store i8* %tmp2, i8** %ptr
+       ret void
+}
+
 define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vst4lanei16:
 ;CHECK: vst4.16