The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / vsub.ll

diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll
index 8f0055fd41037dd0e675b2051e9f3f79f4f09be0..df77bb31fc8b872334633a6d4b5085a5f349d8f6 100644 (file)
--- a/test/CodeGen/ARM/vsub.ll
+++ b/test/CodeGen/ARM/vsub.ll
@@ -41,7 +41,7 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: vsub.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = load <2 x float>* %B
-       %tmp3 = sub <2 x float> %tmp1, %tmp2
+       %tmp3 = fsub <2 x float> %tmp1, %tmp2
        ret <2 x float> %tmp3
 }
 
@@ -86,7 +86,7 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: vsub.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = load <4 x float>* %B
-       %tmp3 = sub <4 x float> %tmp1, %tmp2
+       %tmp3 = fsub <4 x float> %tmp1, %tmp2
        ret <4 x float> %tmp3
 }
 
@@ -157,8 +157,10 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vsubl.s8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
+       %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+       %tmp5 = sub <8 x i16> %tmp3, %tmp4
+       ret <8 x i16> %tmp5
 }
 
 define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -166,8 +168,10 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vsubl.s16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
+       %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+       %tmp5 = sub <4 x i32> %tmp3, %tmp4
+       ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -175,8 +179,10 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vsubl.s32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
+       %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+       %tmp5 = sub <2 x i64> %tmp3, %tmp4
+       ret <2 x i64> %tmp5
 }
 
 define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -184,8 +190,10 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vsubl.u8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
+       %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+       %tmp5 = sub <8 x i16> %tmp3, %tmp4
+       ret <8 x i16> %tmp5
 }
 
 define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -193,8 +201,10 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vsubl.u16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
+       %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+       %tmp5 = sub <4 x i32> %tmp3, %tmp4
+       ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -202,25 +212,20 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vsubl.u32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
+       %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+       %tmp5 = sub <2 x i64> %tmp3, %tmp4
+       ret <2 x i64> %tmp5
 }
 
-declare <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
 define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vsubws8:
 ;CHECK: vsubw.s8
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
+       %tmp4 = sub <8 x i16> %tmp1, %tmp3
+       ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
@@ -228,8 +233,9 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vsubw.s16
        %tmp1 = load <4 x i32>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
+       %tmp4 = sub <4 x i32> %tmp1, %tmp3
+       ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
@@ -237,8 +243,9 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vsubw.s32
        %tmp1 = load <2 x i64>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
+       %tmp4 = sub <2 x i64> %tmp1, %tmp3
+       ret <2 x i64> %tmp4
 }
 
 define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
@@ -246,8 +253,9 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vsubw.u8
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i8>* %B
-       %tmp3 = call <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
-       ret <8 x i16> %tmp3
+       %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
+       %tmp4 = sub <8 x i16> %tmp1, %tmp3
+       ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
@@ -255,8 +263,9 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vsubw.u16
        %tmp1 = load <4 x i32>* %A
        %tmp2 = load <4 x i16>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
-       ret <4 x i32> %tmp3
+       %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
+       %tmp4 = sub <4 x i32> %tmp1, %tmp3
+       ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
@@ -264,14 +273,7 @@ define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vsubw.u32
        %tmp1 = load <2 x i64>* %A
        %tmp2 = load <2 x i32>* %B
-       %tmp3 = call <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
-       ret <2 x i64> %tmp3
+       %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
+       %tmp4 = sub <2 x i64> %tmp1, %tmp3
+       ret <2 x i64> %tmp4
 }
-
-declare <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
-
-declare <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone