-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
-
-%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
-%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
-%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
-%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
-
-%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
-%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
-%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
-%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8:
+;CHECK-LABEL: vtrni8:
;CHECK: vtrn.8
+;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
- %tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrni.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
- %tmp6 = add <8 x i8> %tmp4, %tmp5
- ret <8 x i8> %tmp6
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
}
define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtrni16:
+;CHECK-LABEL: vtrni16:
;CHECK: vtrn.16
+;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
- %tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrni.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
- %tmp6 = add <4 x i16> %tmp4, %tmp5
- ret <4 x i16> %tmp6
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
}
define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtrni32:
+;CHECK-LABEL: vtrni32:
;CHECK: vtrn.32
+;CHECK-NEXT: vadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
- %tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrni.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
- %tmp6 = add <2 x i32> %tmp4, %tmp5
- ret <2 x i32> %tmp6
+ %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
+ %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
}
define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vtrnf:
+;CHECK-LABEL: vtrnf:
;CHECK: vtrn.32
+;CHECK-NEXT: vadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
- %tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrnf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
- %tmp6 = add <2 x float> %tmp4, %tmp5
- ret <2 x float> %tmp6
+ %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
+ %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
+ %tmp5 = fadd <2 x float> %tmp3, %tmp4
+ ret <2 x float> %tmp5
}
define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtrnQi8:
+;CHECK-LABEL: vtrnQi8:
;CHECK: vtrn.8
+;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
- %tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrni.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
- %tmp6 = add <16 x i8> %tmp4, %tmp5
- ret <16 x i8> %tmp6
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
}
define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16:
+;CHECK-LABEL: vtrnQi16:
;CHECK: vtrn.16
+;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
- %tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrni.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
- %tmp6 = add <8 x i16> %tmp4, %tmp5
- ret <8 x i16> %tmp6
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
}
define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtrnQi32:
+;CHECK-LABEL: vtrnQi32:
;CHECK: vtrn.32
+;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
- %tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrni.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
- %tmp6 = add <4 x i32> %tmp4, %tmp5
- ret <4 x i32> %tmp6
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
}
define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vtrnQf:
+;CHECK-LABEL: vtrnQf:
;CHECK: vtrn.32
+;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
- %tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrnf.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- %tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
- %tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
- %tmp6 = add <4 x float> %tmp4, %tmp5
- ret <4 x float> %tmp6
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = fadd <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
+
+; Undef shuffle indices should not prevent matching to VTRN:
+
+define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: vtrni8_undef:
+;CHECK: vtrn.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
}
-declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrni.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrni.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrni.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrnf.v2f32(<2 x float>, <2 x float>) nounwind readnone
+define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: vtrnQi16_undef:
+;CHECK: vtrn.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
-declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrni.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrni.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrni.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrnf.v4f32(<4 x float>, <4 x float>) nounwind readnone
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