Use SCEVAddRecExpr::isAffine.

[oota-llvm.git] / test / CodeGen / Alpha / bsr.ll

diff --git a/test/CodeGen/Alpha/bsr.ll b/test/CodeGen/Alpha/bsr.ll
index 76488bbe251efa0145ece6114b6a470e8d71fe67..d4618577a044403b92b50c2bfb413d9eb163198e 100644 (file)
--- a/test/CodeGen/Alpha/bsr.ll
+++ b/test/CodeGen/Alpha/bsr.ll
@@ -1,15 +1,12 @@
 ; Make sure this testcase codegens the bsr instruction
-; RUN: llvm-as < %s | llc -march=alpha | grep 'bsr'
+; RUN: llvm-as < %s | llc -march=alpha | grep bsr
 
-
-implementation   ; Functions:
-
-long %abc(int %x) {
-entry:
-       %tmp.2 = add int %x, -1         ; <int> [#uses=1]
-       %tmp.0 = call long %abc( int %tmp.2 )           ; <long> [#uses=1]
-       %tmp.5 = add int %x, -2         ; <int> [#uses=1]
-       %tmp.3 = call long %abc( int %tmp.5 )           ; <long> [#uses=1]
-       %tmp.6 = add long %tmp.0, %tmp.3                ; <long> [#uses=1]
-       ret long %tmp.6
+define internal i64 @abc(i32 %x) {
+        %tmp.2 = add i32 %x, -1         ; <i32> [#uses=1]
+        %tmp.0 = call i64 @abc( i32 %tmp.2 )            ; <i64> [#uses=1]
+        %tmp.5 = add i32 %x, -2         ; <i32> [#uses=1]
+        %tmp.3 = call i64 @abc( i32 %tmp.5 )            ; <i64> [#uses=1]
+        %tmp.6 = add i64 %tmp.0, %tmp.3         ; <i64> [#uses=1]
+        ret i64 %tmp.6
 }
+