Use SCEVAddRecExpr::isAffine.

[oota-llvm.git] / test / CodeGen / Alpha / ctlz.ll

diff --git a/test/CodeGen/Alpha/ctlz.ll b/test/CodeGen/Alpha/ctlz.ll
index c99d60e08d553a6f78850fc7d6badffb22d4ae24..83d97b5833c46efb947d2cc712c9a597d8f560aa 100644 (file)
--- a/test/CodeGen/Alpha/ctlz.ll
+++ b/test/CodeGen/Alpha/ctlz.ll
@@ -1,12 +1,14 @@
 ; Make sure this testcase codegens to the ctlz instruction
-; RUN: llvm-as < %s | llc -march=alpha -enable-alpha-CT | grep 'ctlz'
+; RUN: llvm-as < %s | llc -march=alpha -mcpu=ev67 | grep -i ctlz
+; RUN: llvm-as < %s | llc -march=alpha -mattr=+CIX | grep -i ctlz
+; RUN: llvm-as < %s | llc -march=alpha -mcpu=ev6 | not grep -i ctlz
+; RUN: llvm-as < %s | llc -march=alpha -mattr=-CIX | not grep -i ctlz
 
-declare ubyte %llvm.ctlz(ubyte)
+declare i8 @llvm.ctlz.i8(i8)
 
-implementation   ; Functions:
-
-ubyte %bar(ubyte %x) {
+define i32 @bar(i8 %x) {
 entry:
-       %tmp.1 = call ubyte %llvm.ctlz( ubyte %x ) 
-       ret ubyte %tmp.1
+       %tmp.1 = call i8 @llvm.ctlz.i8( i8 %x ) 
+       %tmp.2 = sext i8 %tmp.1 to i32
+       ret i32 %tmp.2
 }