Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / 2009-01-01-BrCond.ll

diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
index 3002bbc2517e67f787c98014659cc506dcfcd96e..35422311c57433c836143b6e4d1b93ae673f623b 100644 (file)
--- a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
+++ b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brz
+; RUN: llc < %s -march=cellspu -o - | grep brz
 ; PR3274
 
 target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
@@ -8,11 +8,11 @@ target triple = "spu"
 
 define double @__floatunsidf(i32 %arg_a) nounwind {
 entry:
-       %in = alloca %struct.fp_number_type, align 8            ; <%struct.fp_number_type*> [#uses=5]
-       %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1            ; <i32*> [#uses=1]
+       %in = alloca %struct.fp_number_type, align 16
+       %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1
        store i32 0, i32* %0, align 4
-       %1 = icmp eq i32 %arg_a, 0              ; <i1> [#uses=1]
-       %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0            ; <i32*> [#uses=2]
+       %1 = icmp eq i32 %arg_a, 0
+       %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0
        br i1 %1, label %bb, label %bb1
 
 bb:            ; preds = %entry
@@ -26,6 +26,6 @@ bb7:          ; preds = %bb5, %bb1, %bb
        ret double 1.0
 }
 
-declare i32 @llvm.ctlz.i32(i32) nounwind readnone
+; declare i32 @llvm.ctlz.i32(i32) nounwind readnone
 
 declare double @__pack_d(%struct.fp_number_type*)