Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / ctpop.ll

diff --git a/test/CodeGen/CellSPU/ctpop.ll b/test/CodeGen/CellSPU/ctpop.ll
index 79bb611fe20a315f6186fffc8a6ba2e8c95b5eeb..e1a6cd829260f77aa2b92c20ce7bfc463c3b7ab4 100644 (file)
--- a/test/CodeGen/CellSPU/ctpop.ll
+++ b/test/CodeGen/CellSPU/ctpop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep cntb    %t1.s | count 3
 ; RUN: grep andi    %t1.s | count 3
 ; RUN: grep rotmi   %t1.s | count 2
@@ -6,19 +6,19 @@
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 
-declare i32 @llvm.ctpop.i8(i8)
-declare i32 @llvm.ctpop.i16(i16)
+declare i8 @llvm.ctpop.i8(i8)
+declare i16 @llvm.ctpop.i16(i16)
 declare i32 @llvm.ctpop.i32(i32)
 
 define i32 @test_i8(i8 %X) {
-        call i32 @llvm.ctpop.i8(i8 %X)
-        %Y = bitcast i32 %1 to i32
+        call i8 @llvm.ctpop.i8(i8 %X)
+        %Y = zext i8 %1 to i32
         ret i32 %Y
 }
 
 define i32 @test_i16(i16 %X) {
-        call i32 @llvm.ctpop.i16(i16 %X)
-        %Y = bitcast i32 %1 to i32
+        call i16 @llvm.ctpop.i16(i16 %X)
+        %Y = zext i16 %1 to i32
         ret i32 %Y
 }