Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / extract_elt.ll

diff --git a/test/CodeGen/CellSPU/extract_elt.ll b/test/CodeGen/CellSPU/extract_elt.ll
index 0987e2b5beccd9cf9d316fd85c0c2b50be339369..0ac971c58c5b8a9eefab9359f701602ae9a761c5 100644 (file)
--- a/test/CodeGen/CellSPU/extract_elt.ll
+++ b/test/CodeGen/CellSPU/extract_elt.ll
@@ -1,9 +1,9 @@
-; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep shufb   %t1.s | count 39
 ; RUN: grep ilhu    %t1.s | count 27
 ; RUN: grep iohl    %t1.s | count 27
 ; RUN: grep lqa     %t1.s | count 10
-; RUN: grep shlqbyi %t1.s | count 12
+; RUN: grep shlqby  %t1.s | count 12
 ; RUN: grep   515   %t1.s | count 1
 ; RUN: grep  1029   %t1.s | count 2
 ; RUN: grep  1543   %t1.s | count 2
@@ -28,7 +28,6 @@
 ; RUN: grep 32782   %t1.s | count 1
 ; RUN: grep 32783   %t1.s | count 1
 ; RUN: grep 32896   %t1.s | count 24
-; XFAIL: *
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"