Add necessary 64-bit support so that gcc frontend compiles (mostly). Current

[oota-llvm.git] / test / CodeGen / CellSPU / fdiv.ll

diff --git a/test/CodeGen/CellSPU/fdiv.ll b/test/CodeGen/CellSPU/fdiv.ll
index a107bbe1f739c99289ddef4725b565c1ff94fcf5..75af90e23f88541ea67f50942c677b096233198a 100644 (file)
--- a/test/CodeGen/CellSPU/fdiv.ll
+++ b/test/CodeGen/CellSPU/fdiv.ll
@@ -1,8 +1,8 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep frest    %t1.s | count 2 &&
-; RUN: grep fi       %t1.s | count 2 &&
-; RUN: grep fm       %t1.s | count 4 &&
-; RUN: grep fma      %t1.s | count 2 &&
+; RUN: grep frest    %t1.s | count 2 
+; RUN: grep fi       %t1.s | count 2 
+; RUN: grep fm       %t1.s | count 4 
+; RUN: grep fma      %t1.s | count 2 
 ; RUN: grep fnms     %t1.s | count 2
 ;
 ; This file includes standard floating point arithmetic instructions
@@ -10,11 +10,11 @@ target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i
 target triple = "spu"
 
 define float @fdiv32(float %arg1, float %arg2) {
-       %A = fdiv float %arg1,  %arg2
-       ret float %A
+        %A = fdiv float %arg1,  %arg2
+        ret float %A
 }
 
 define <4 x float> @fdiv_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
-       %A = fdiv <4 x float> %arg1,  %arg2
-       ret <4 x float> %A
+        %A = fdiv <4 x float> %arg1,  %arg2
+        ret <4 x float> %A
 }