Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / icmp32.ll

diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll
index ccbb5f7cde580971689cf929c0a3910dd06ece3c..1794f4cd7b66d95e6636bf956a15138ed27435d0 100644 (file)
--- a/test/CodeGen/CellSPU/icmp32.ll
+++ b/test/CodeGen/CellSPU/icmp32.ll
@@ -1,14 +1,4 @@
-; RUN: llc < %s -march=cellspu > %t1.s
-; RUN: grep ila                                %t1.s | count 6
-; RUN: grep ceq                                %t1.s | count 28
-; RUN: grep ceqi                               %t1.s | count 12
-; RUN: grep clgt                               %t1.s | count 16
-; RUN: grep clgti                              %t1.s | count 6
-; RUN: grep cgt                                %t1.s | count 16
-; RUN: grep cgti                               %t1.s | count 6
-; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
-; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
-; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 20
+; RUN: llc < %s -march=cellspu | FileCheck %s
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
@@ -27,6 +17,10 @@ target triple = "spu"
 
 ; i32 integer comparisons:
 define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_select_i32:
+; CHECK:        ceq
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp eq i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -34,12 +28,22 @@ entry:
 }
 
 define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_setcc_i32:
+; CHECK:        ilhu
+; CHECK:        ceq
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp eq i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_immed01_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp eq i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -47,6 +51,10 @@ entry:
 }
 
 define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_immed02_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp eq i32 %arg1, -512
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -54,6 +62,10 @@ entry:
 }
 
 define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_immed03_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp eq i32 %arg1, -1
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -61,6 +73,11 @@ entry:
 }
 
 define i32 @icmp_eq_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_eq_immed04_i32:
+; CHECK:        ila
+; CHECK:        ceq
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp eq i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -68,6 +85,10 @@ entry:
 }
 
 define i32 @icmp_ne_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_select_i32:
+; CHECK:        ceq
+; CHECK:        selb $3, $5, $6, $3
+
 entry:
        %A = icmp ne i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -75,12 +96,23 @@ entry:
 }
 
 define i1 @icmp_ne_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_setcc_i32:
+; CHECK:        ceq
+; CHECK:        ilhu
+; CHECK:        xori
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp ne i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_ne_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_immed01_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $4, $5, $3
+
 entry:
        %A = icmp ne i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -88,6 +120,10 @@ entry:
 }
 
 define i32 @icmp_ne_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_immed02_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $4, $5, $3
+
 entry:
        %A = icmp ne i32 %arg1, -512
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -95,6 +131,10 @@ entry:
 }
 
 define i32 @icmp_ne_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_immed03_i32:
+; CHECK:        ceqi
+; CHECK:        selb $3, $4, $5, $3
+
 entry:
        %A = icmp ne i32 %arg1, -1
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -102,6 +142,11 @@ entry:
 }
 
 define i32 @icmp_ne_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ne_immed04_i32:
+; CHECK:        ila
+; CHECK:        ceq
+; CHECK:        selb $3, $4, $5, $3
+
 entry:
        %A = icmp ne i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -109,6 +154,10 @@ entry:
 }
 
 define i32 @icmp_ugt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_select_i32:
+; CHECK:        clgt
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp ugt i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -116,12 +165,22 @@ entry:
 }
 
 define i1 @icmp_ugt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_setcc_i32:
+; CHECK:        ilhu
+; CHECK:        clgt
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp ugt i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_ugt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_immed01_i32:
+; CHECK:        clgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ugt i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -129,6 +188,10 @@ entry:
 }
 
 define i32 @icmp_ugt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_immed02_i32:
+; CHECK:        clgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ugt i32 %arg1, 4294966784
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -136,6 +199,10 @@ entry:
 }
 
 define i32 @icmp_ugt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_immed03_i32:
+; CHECK:        clgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ugt i32 %arg1, 4294967293
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -143,6 +210,11 @@ entry:
 }
 
 define i32 @icmp_ugt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ugt_immed04_i32:
+; CHECK:        ila
+; CHECK:        clgt
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ugt i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -150,6 +222,12 @@ entry:
 }
 
 define i32 @icmp_uge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_uge_select_i32:
+; CHECK:        ceq
+; CHECK:        clgt
+; CHECK:        or
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp uge i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -157,6 +235,14 @@ entry:
 }
 
 define i1 @icmp_uge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_uge_setcc_i32:
+; CHECK:        ceq
+; CHECK:        clgt
+; CHECK:        ilhu
+; CHECK:        or
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp uge i32 %arg1, %arg2
        ret i1 %A
@@ -169,6 +255,12 @@ entry:
 ;; they'll ever be generated.
 
 define i32 @icmp_ult_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_select_i32:
+; CHECK:        ceq
+; CHECK:        clgt
+; CHECK:        nor
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp ult i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -176,12 +268,26 @@ entry:
 }
 
 define i1 @icmp_ult_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_setcc_i32:
+; CHECK:        ceq
+; CHECK:        clgt
+; CHECK:        ilhu
+; CHECK:        nor
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp ult i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_ult_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_immed01_i32:
+; CHECK:        ceqi
+; CHECK:        clgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ult i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -189,6 +295,12 @@ entry:
 }
 
 define i32 @icmp_ult_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_immed02_i32:
+; CHECK:        ceqi
+; CHECK:        clgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ult i32 %arg1, 4294966784
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -196,6 +308,12 @@ entry:
 }
 
 define i32 @icmp_ult_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_immed03_i32:
+; CHECK:        ceqi
+; CHECK:        clgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ult i32 %arg1, 4294967293
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -203,6 +321,11 @@ entry:
 }
 
 define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ult_immed04_i32:
+; CHECK:        rotmi
+; CHECK:        ceqi
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp ult i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -210,6 +333,10 @@ entry:
 }
 
 define i32 @icmp_ule_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ule_select_i32:
+; CHECK:        clgt
+; CHECK:        selb $3, $5, $6, $3
+
 entry:
        %A = icmp ule i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -217,6 +344,13 @@ entry:
 }
 
 define i1 @icmp_ule_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_ule_setcc_i32:
+; CHECK:        clgt
+; CHECK:        ilhu
+; CHECK:        xori
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp ule i32 %arg1, %arg2
        ret i1 %A
@@ -229,6 +363,10 @@ entry:
 ;; they'll ever be generated.
 
 define i32 @icmp_sgt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_select_i32:
+; CHECK:        cgt
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp sgt i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -236,12 +374,22 @@ entry:
 }
 
 define i1 @icmp_sgt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_setcc_i32:
+; CHECK:        ilhu
+; CHECK:        cgt
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp sgt i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_sgt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_immed01_i32:
+; CHECK:        cgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp sgt i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -249,6 +397,10 @@ entry:
 }
 
 define i32 @icmp_sgt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_immed02_i32:
+; CHECK:        cgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp sgt i32 %arg1, 4294966784
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -256,6 +408,10 @@ entry:
 }
 
 define i32 @icmp_sgt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_immed03_i32:
+; CHECK:        cgti
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp sgt i32 %arg1, 4294967293
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -263,6 +419,11 @@ entry:
 }
 
 define i32 @icmp_sgt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sgt_immed04_i32:
+; CHECK:        ila
+; CHECK:        cgt
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp sgt i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -270,6 +431,12 @@ entry:
 }
 
 define i32 @icmp_sge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sge_select_i32:
+; CHECK:        ceq
+; CHECK:        cgt
+; CHECK:        or
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp sge i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -277,6 +444,14 @@ entry:
 }
 
 define i1 @icmp_sge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sge_setcc_i32:
+; CHECK:        ceq
+; CHECK:        cgt
+; CHECK:        ilhu
+; CHECK:        or
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp sge i32 %arg1, %arg2
        ret i1 %A
@@ -289,6 +464,12 @@ entry:
 ;; they'll ever be generated.
 
 define i32 @icmp_slt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_select_i32:
+; CHECK:        ceq
+; CHECK:        cgt
+; CHECK:        nor
+; CHECK:        selb $3, $6, $5, $3
+
 entry:
        %A = icmp slt i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -296,12 +477,26 @@ entry:
 }
 
 define i1 @icmp_slt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_setcc_i32:
+; CHECK:        ceq
+; CHECK:        cgt
+; CHECK:        ilhu
+; CHECK:        nor
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp slt i32 %arg1, %arg2
        ret i1 %A
 }
 
 define i32 @icmp_slt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_immed01_i32:
+; CHECK:        ceqi
+; CHECK:        cgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp slt i32 %arg1, 511
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -309,6 +504,12 @@ entry:
 }
 
 define i32 @icmp_slt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_immed02_i32:
+; CHECK:        ceqi
+; CHECK:        cgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp slt i32 %arg1, -512
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -316,6 +517,12 @@ entry:
 }
 
 define i32 @icmp_slt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_immed03_i32:
+; CHECK:        ceqi
+; CHECK:        cgti
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp slt i32 %arg1, -1
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -323,6 +530,13 @@ entry:
 }
 
 define i32 @icmp_slt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_slt_immed04_i32:
+; CHECK:        ila
+; CHECK:        ceq
+; CHECK:        cgt
+; CHECK:        nor
+; CHECK:        selb $3, $5, $4, $3
+
 entry:
        %A = icmp slt i32 %arg1, 32768
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -330,6 +544,10 @@ entry:
 }
 
 define i32 @icmp_sle_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sle_select_i32:
+; CHECK:        cgt
+; CHECK:        selb $3, $5, $6, $3
+
 entry:
        %A = icmp sle i32 %arg1, %arg2
        %B = select i1 %A, i32 %val1, i32 %val2
@@ -337,6 +555,13 @@ entry:
 }
 
 define i1 @icmp_sle_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+; CHECK:      icmp_sle_setcc_i32:
+; CHECK:        cgt
+; CHECK:        ilhu
+; CHECK:        xori
+; CHECK:        iohl
+; CHECK:        shufb
+
 entry:
        %A = icmp sle i32 %arg1, %arg2
        ret i1 %A