Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / loads.ll

diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
index c46bcd18c15af5473f023130a71f0cf61c22cde2..4771752f5f4c7954b9471c9aa298d45add25bf2d 100644 (file)
--- a/test/CodeGen/CellSPU/loads.ll
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -22,17 +22,38 @@ entry:
 
 declare <4 x i32>* @getv4f32ptr()
 define <4 x i32> @func() {
-        ;CHECK: brasl
-        ;CHECK: lr     {{\$[0-9]*, \$3}}
-        ;CHECK: brasl
-        %rv1 = call <4 x i32>* @getv4f32ptr()
-        %rv2 = call <4 x i32>* @getv4f32ptr()
-        %rv3 = load <4 x i32>* %rv1
-        ret <4 x i32> %rv3
+       ;CHECK: brasl
+       ; we need to have some instruction to move the result to safety.
+       ; which instruction (lr, stqd...) depends on the regalloc
+       ;CHECK: {{.*}}
+       ;CHECK: brasl
+       %rv1 = call <4 x i32>* @getv4f32ptr()
+       %rv2 = call <4 x i32>* @getv4f32ptr()
+       %rv3 = load <4 x i32>* %rv1
+       ret <4 x i32> %rv3
 }
 
 define <4 x float> @load_undef(){
-       ;CHECK lqd      $3, 0($3)
+       ; CHECK: lqd    $3, 0($3)
        %val = load <4 x float>* undef
        ret <4 x float> %val
 }
+
+;check that 'misaligned' loads that may span two memory chunks
+;have two loads. Don't check for the bitmanipulation, as that 
+;might change with improved algorithms or scheduling 
+define i32 @load_misaligned( i32* %ptr ){
+;CHECK: load_misaligned
+;CHECK: lqd
+;CHECK: lqd
+;CHECK: bi $lr
+  %rv = load i32* %ptr, align 2
+  ret i32 %rv
+}
+
+define <4 x i32> @load_null_vec( ) {
+;CHECK: lqa
+;CHECK: bi $lr
+       %rv = load <4 x i32>* null
+       ret <4 x i32> %rv
+}