Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / mul-with-overflow.ll

diff --git a/test/CodeGen/CellSPU/mul-with-overflow.ll b/test/CodeGen/CellSPU/mul-with-overflow.ll
index d15da12649eade00dc769b83d3fd41c8b9d3dc44..c04e69e3e193da5bce22aa96ee7994977fb17204 100644 (file)
--- a/test/CodeGen/CellSPU/mul-with-overflow.ll
+++ b/test/CodeGen/CellSPU/mul-with-overflow.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=cellspu
 
 declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b)
-define i1 @a(i16 %x) zeroext nounwind {
+define zeroext i1 @a(i16 %x)  nounwind {
   %res = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %x, i16 3)
   %obil = extractvalue {i16, i1} %res, 1
   ret i1 %obil
 }
 
 declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b)
-define i1 @b(i16 %x) zeroext nounwind {
+define zeroext i1 @b(i16 %x)  nounwind {
   %res = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 3)
   %obil = extractvalue {i16, i1} %res, 1
   ret i1 %obil