Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / mul_ops.ll

diff --git a/test/CodeGen/CellSPU/mul_ops.ll b/test/CodeGen/CellSPU/mul_ops.ll
index e1509d27cba5fad887911a16173b4fec0092a6c5..1e28fc7a918d23bd161cb44d40640d366d04b96c 100644 (file)
--- a/test/CodeGen/CellSPU/mul_ops.ll
+++ b/test/CodeGen/CellSPU/mul_ops.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep mpy     %t1.s | count 44
 ; RUN: grep mpyu    %t1.s | count 4
 ; RUN: grep mpyh    %t1.s | count 10
@@ -11,8 +11,6 @@
 ; RUN: grep shli    %t1.s | count 4
 ; RUN: grep shlhi   %t1.s | count 4
 ; RUN: grep ila     %t1.s | count 2
-; RUN: grep xsbh    %t1.s | count 8
-; RUN: grep xshw    %t1.s | count 4
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 
@@ -55,36 +53,36 @@ entry:
 
 define i32 @mul_i32_1(i32 %arg1, i32 %arg2) {
 entry:
-       %A = mul i32 %arg2, %arg1
-       ret i32 %A
+        %A = mul i32 %arg2, %arg1
+        ret i32 %A
 }
 
 define i32 @mul_i32_2(i32 %arg1, i32 %arg2) {
 entry:
-       %A = mul i32 %arg1, %arg2
-       ret i32 %A
+        %A = mul i32 %arg1, %arg2
+        ret i32 %A
 }
 
 define i16 @mul_i16_1(i16 %arg1, i16 %arg2) {
 entry:
-       %A = mul i16 %arg2, %arg1
-       ret i16 %A
+        %A = mul i16 %arg2, %arg1
+        ret i16 %A
 }
 
 define i16 @mul_i16_2(i16 %arg1, i16 %arg2) {
 entry:
-       %A = mul i16 %arg1, %arg2
-       ret i16 %A
+        %A = mul i16 %arg1, %arg2
+        ret i16 %A
 }
 
 define i8 @mul_i8_1(i8 %arg1, i8 %arg2) {
 entry:
-       %A = mul i8 %arg2, %arg1
-       ret i8 %A
+        %A = mul i8 %arg2, %arg1
+        ret i8 %A
 }
 
 define i8 @mul_i8_2(i8 %arg1, i8 %arg2) {
 entry:
-       %A = mul i8 %arg1, %arg2
-       ret i8 %A
+        %A = mul i8 %arg1, %arg2
+        ret i8 %A
 }