Fix a cycle in the DAG. In this code we replace multiple loads with a single load and

[oota-llvm.git] / test / CodeGen / CellSPU / stores.ll

diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
index efc915ca2691ab71912a4c25141b52966e12c96b..43f8776a3d46597c0bce46600e35aca9af1262d9 100644 (file)
--- a/test/CodeGen/CellSPU/stores.ll
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
-; RUN: grep {stqd.*0(\$3)}      %t1.s | count 4
-; RUN: grep {stqd.*16(\$3)}     %t1.s | count 4
+; RUN: grep 'stqd.*0($3)'       %t1.s | count 4
+; RUN: grep 'stqd.*16($3)'      %t1.s | count 4
 ; RUN: grep 16256               %t1.s | count 2
 ; RUN: grep 16384               %t1.s | count 1
 ; RUN: grep 771                 %t1.s | count 4
@@ -8,7 +8,7 @@
 ; RUN: grep 1799                %t1.s | count 2
 ; RUN: grep 1543                %t1.s | count 5
 ; RUN: grep 1029                %t1.s | count 3
-; RUN: grep {shli.*, 4}         %t1.s | count 4
+; RUN: grep 'shli.*, 4'         %t1.s | count 4
 ; RUN: grep stqx                %t1.s | count 4
 ; RUN: grep ilhu                %t1.s | count 11
 ; RUN: grep iohl                %t1.s | count 8
@@ -162,3 +162,20 @@ define void @store_misaligned( i32 %val, i32* %ptr) {
        store i32 %val, i32*%ptr, align 2
        ret void
 }
+
+define void @store_v8( <8 x float> %val, <8 x float>* %ptr )
+{
+;CHECK: stq
+;CHECK: stq
+;CHECK: bi $lr
+       store <8 x float> %val, <8 x float>* %ptr
+       ret void
+}
+
+define void @store_null_vec( <4 x i32> %val ) {
+; FIXME - this is for some reason compiled into a il+stqd, not a sta. 
+;CHECK: stqd
+;CHECK: bi $lr
+       store <4 x i32> %val, <4 x i32>* null
+       ret void
+}