Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / CellSPU / v2f32.ll

diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll
index b32c23b4280db57c8c9ddc771103bed7247b0d43..09e15ffbc75d0f55bf163a099ebcb387b96cb7a2 100644 (file)
--- a/test/CodeGen/CellSPU/v2f32.ll
+++ b/test/CodeGen/CellSPU/v2f32.ll
@@ -9,7 +9,7 @@ define %vec @test_ret(%vec %param)
 
 define %vec @test_add(%vec %param)
 {
-;CHECK: fa $3, $3, $3
+;CHECK: fa {{\$.}}, $3, $3
  %1 = fadd %vec %param, %param
 ;CHECK: bi $lr
  ret %vec %1
@@ -17,7 +17,7 @@ define %vec @test_add(%vec %param)
 
 define %vec @test_sub(%vec %param)
 {
-;CHECK: fs $3, $3, $3
+;CHECK: fs {{\$.}}, $3, $3
  %1 = fsub %vec %param, %param
 
 ;CHECK: bi $lr
@@ -26,13 +26,14 @@ define %vec @test_sub(%vec %param)
 
 define %vec @test_mul(%vec %param)
 {
-;CHECK: fm $3, $3, $3
+;CHECK: fm {{\$.}}, $3, $3
  %1 = fmul %vec %param, %param
 
 ;CHECK: bi $lr
  ret %vec %1
 }
 
+; CHECK: test_splat:
 define %vec @test_splat(float %param ) {
 ;CHECK: lqa
 ;CHECK: shufb
@@ -43,16 +44,17 @@ define %vec @test_splat(float %param ) {
 }
 
 define void @test_store(%vec %val, %vec* %ptr){
-
+; CHECK: test_store:
 ;CHECK: stqd 
-  store %vec undef, %vec* null
+  store %vec zeroinitializer, %vec* null
 
-;CHECK: stqd $3, 0($4)
+;CHECK: stqd $3, 0(${{.*}})
 ;CHECK: bi $lr
   store %vec %val, %vec* %ptr
   ret void
 }
 
+; CHECK: test_insert:
 define %vec @test_insert(){
 ;CHECK: cwd
 ;CHECK: shufb $3
@@ -61,3 +63,16 @@ define %vec @test_insert(){
   ret %vec %rv
 }
 
+; CHECK: test_unaligned_store:
+
+define void @test_unaligned_store()  {
+;CHECK:        cdd
+;CHECK:        shufb
+;CHECK:        stqd
+  %data = alloca [4 x float], align 16         ; <[4 x float]*> [#uses=1]
+  %ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1]
+  %vptr = bitcast float* %ptr to  <2 x float>* ; <[1 x <2 x float>]*> [#uses=1]
+  store <2 x float> zeroinitializer, <2 x float>* %vptr
+  ret void
+}
+